544 lines
13 KiB
C
544 lines
13 KiB
C
/*
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* Intel SMP support routines.
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*
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* (c) 1995 Alan Cox, Building #3 <alan@redhat.com>
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* (c) 1998-99, 2000 Ingo Molnar <mingo@redhat.com>
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* (c) 2002,2003 Andi Kleen, SuSE Labs.
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*
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* This code is released under the GNU General Public License version 2 or
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* later.
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*/
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#include <linux/init.h>
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#include <linux/mm.h>
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#include <linux/delay.h>
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#include <linux/spinlock.h>
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#include <linux/smp_lock.h>
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#include <linux/smp.h>
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#include <linux/kernel_stat.h>
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#include <linux/mc146818rtc.h>
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#include <linux/interrupt.h>
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#include <asm/mtrr.h>
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#include <asm/pgalloc.h>
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#include <asm/tlbflush.h>
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#include <asm/mach_apic.h>
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#include <asm/mmu_context.h>
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#include <asm/proto.h>
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#include <asm/apicdef.h>
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#include <asm/idle.h>
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/*
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* Smarter SMP flushing macros.
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* c/o Linus Torvalds.
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*
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* These mean you can really definitely utterly forget about
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* writing to user space from interrupts. (Its not allowed anyway).
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*
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* Optimizations Manfred Spraul <manfred@colorfullife.com>
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*
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* More scalable flush, from Andi Kleen
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*
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* To avoid global state use 8 different call vectors.
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* Each CPU uses a specific vector to trigger flushes on other
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* CPUs. Depending on the received vector the target CPUs look into
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* the right per cpu variable for the flush data.
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*
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* With more than 8 CPUs they are hashed to the 8 available
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* vectors. The limited global vector space forces us to this right now.
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* In future when interrupts are split into per CPU domains this could be
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* fixed, at the cost of triggering multiple IPIs in some cases.
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*/
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union smp_flush_state {
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struct {
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cpumask_t flush_cpumask;
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struct mm_struct *flush_mm;
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unsigned long flush_va;
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#define FLUSH_ALL -1ULL
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spinlock_t tlbstate_lock;
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};
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char pad[SMP_CACHE_BYTES];
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} ____cacheline_aligned;
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/* State is put into the per CPU data section, but padded
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to a full cache line because other CPUs can access it and we don't
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want false sharing in the per cpu data segment. */
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static DEFINE_PER_CPU(union smp_flush_state, flush_state);
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/*
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* We cannot call mmdrop() because we are in interrupt context,
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* instead update mm->cpu_vm_mask.
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*/
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static inline void leave_mm(int cpu)
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{
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if (read_pda(mmu_state) == TLBSTATE_OK)
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BUG();
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cpu_clear(cpu, read_pda(active_mm)->cpu_vm_mask);
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load_cr3(swapper_pg_dir);
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}
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/*
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*
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* The flush IPI assumes that a thread switch happens in this order:
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* [cpu0: the cpu that switches]
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* 1) switch_mm() either 1a) or 1b)
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* 1a) thread switch to a different mm
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* 1a1) cpu_clear(cpu, old_mm->cpu_vm_mask);
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* Stop ipi delivery for the old mm. This is not synchronized with
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* the other cpus, but smp_invalidate_interrupt ignore flush ipis
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* for the wrong mm, and in the worst case we perform a superfluous
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* tlb flush.
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* 1a2) set cpu mmu_state to TLBSTATE_OK
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* Now the smp_invalidate_interrupt won't call leave_mm if cpu0
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* was in lazy tlb mode.
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* 1a3) update cpu active_mm
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* Now cpu0 accepts tlb flushes for the new mm.
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* 1a4) cpu_set(cpu, new_mm->cpu_vm_mask);
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* Now the other cpus will send tlb flush ipis.
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* 1a4) change cr3.
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* 1b) thread switch without mm change
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* cpu active_mm is correct, cpu0 already handles
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* flush ipis.
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* 1b1) set cpu mmu_state to TLBSTATE_OK
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* 1b2) test_and_set the cpu bit in cpu_vm_mask.
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* Atomically set the bit [other cpus will start sending flush ipis],
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* and test the bit.
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* 1b3) if the bit was 0: leave_mm was called, flush the tlb.
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* 2) switch %%esp, ie current
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*
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* The interrupt must handle 2 special cases:
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* - cr3 is changed before %%esp, ie. it cannot use current->{active_,}mm.
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* - the cpu performs speculative tlb reads, i.e. even if the cpu only
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* runs in kernel space, the cpu could load tlb entries for user space
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* pages.
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*
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* The good news is that cpu mmu_state is local to each cpu, no
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* write/read ordering problems.
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*/
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/*
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* TLB flush IPI:
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*
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* 1) Flush the tlb entries if the cpu uses the mm that's being flushed.
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* 2) Leave the mm if we are in the lazy tlb mode.
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*
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* Interrupts are disabled.
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*/
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asmlinkage void smp_invalidate_interrupt(struct pt_regs *regs)
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{
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int cpu;
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int sender;
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union smp_flush_state *f;
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cpu = smp_processor_id();
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/*
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* orig_rax contains the interrupt vector - 256.
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* Use that to determine where the sender put the data.
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*/
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sender = regs->orig_rax + 256 - INVALIDATE_TLB_VECTOR_START;
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f = &per_cpu(flush_state, sender);
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if (!cpu_isset(cpu, f->flush_cpumask))
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goto out;
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/*
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* This was a BUG() but until someone can quote me the
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* line from the intel manual that guarantees an IPI to
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* multiple CPUs is retried _only_ on the erroring CPUs
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* its staying as a return
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*
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* BUG();
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*/
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if (f->flush_mm == read_pda(active_mm)) {
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if (read_pda(mmu_state) == TLBSTATE_OK) {
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if (f->flush_va == FLUSH_ALL)
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local_flush_tlb();
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else
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__flush_tlb_one(f->flush_va);
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} else
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leave_mm(cpu);
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}
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out:
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ack_APIC_irq();
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cpu_clear(cpu, f->flush_cpumask);
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}
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static void flush_tlb_others(cpumask_t cpumask, struct mm_struct *mm,
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unsigned long va)
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{
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int sender;
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union smp_flush_state *f;
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/* Caller has disabled preemption */
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sender = smp_processor_id() % NUM_INVALIDATE_TLB_VECTORS;
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f = &per_cpu(flush_state, sender);
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/* Could avoid this lock when
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num_online_cpus() <= NUM_INVALIDATE_TLB_VECTORS, but it is
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probably not worth checking this for a cache-hot lock. */
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spin_lock(&f->tlbstate_lock);
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f->flush_mm = mm;
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f->flush_va = va;
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cpus_or(f->flush_cpumask, cpumask, f->flush_cpumask);
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/*
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* We have to send the IPI only to
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* CPUs affected.
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*/
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send_IPI_mask(cpumask, INVALIDATE_TLB_VECTOR_START + sender);
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while (!cpus_empty(f->flush_cpumask))
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cpu_relax();
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f->flush_mm = NULL;
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f->flush_va = 0;
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spin_unlock(&f->tlbstate_lock);
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}
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int __cpuinit init_smp_flush(void)
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{
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int i;
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for_each_cpu_mask(i, cpu_possible_map) {
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spin_lock_init(&per_cpu(flush_state.tlbstate_lock, i));
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}
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return 0;
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}
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core_initcall(init_smp_flush);
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void flush_tlb_current_task(void)
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{
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struct mm_struct *mm = current->mm;
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cpumask_t cpu_mask;
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preempt_disable();
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cpu_mask = mm->cpu_vm_mask;
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cpu_clear(smp_processor_id(), cpu_mask);
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local_flush_tlb();
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if (!cpus_empty(cpu_mask))
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flush_tlb_others(cpu_mask, mm, FLUSH_ALL);
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preempt_enable();
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}
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void flush_tlb_mm (struct mm_struct * mm)
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{
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cpumask_t cpu_mask;
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preempt_disable();
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cpu_mask = mm->cpu_vm_mask;
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cpu_clear(smp_processor_id(), cpu_mask);
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if (current->active_mm == mm) {
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if (current->mm)
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local_flush_tlb();
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else
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leave_mm(smp_processor_id());
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}
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if (!cpus_empty(cpu_mask))
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flush_tlb_others(cpu_mask, mm, FLUSH_ALL);
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preempt_enable();
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}
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void flush_tlb_page(struct vm_area_struct * vma, unsigned long va)
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{
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struct mm_struct *mm = vma->vm_mm;
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cpumask_t cpu_mask;
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preempt_disable();
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cpu_mask = mm->cpu_vm_mask;
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cpu_clear(smp_processor_id(), cpu_mask);
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if (current->active_mm == mm) {
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if(current->mm)
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__flush_tlb_one(va);
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else
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leave_mm(smp_processor_id());
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}
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if (!cpus_empty(cpu_mask))
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flush_tlb_others(cpu_mask, mm, va);
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preempt_enable();
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}
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static void do_flush_tlb_all(void* info)
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{
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unsigned long cpu = smp_processor_id();
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__flush_tlb_all();
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if (read_pda(mmu_state) == TLBSTATE_LAZY)
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leave_mm(cpu);
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}
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void flush_tlb_all(void)
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{
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on_each_cpu(do_flush_tlb_all, NULL, 1, 1);
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}
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/*
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* this function sends a 'reschedule' IPI to another CPU.
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* it goes straight through and wastes no time serializing
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* anything. Worst case is that we lose a reschedule ...
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*/
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void smp_send_reschedule(int cpu)
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{
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send_IPI_mask(cpumask_of_cpu(cpu), RESCHEDULE_VECTOR);
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}
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/*
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* Structure and data for smp_call_function(). This is designed to minimise
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* static memory requirements. It also looks cleaner.
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*/
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static DEFINE_SPINLOCK(call_lock);
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struct call_data_struct {
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void (*func) (void *info);
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void *info;
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atomic_t started;
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atomic_t finished;
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int wait;
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};
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static struct call_data_struct * call_data;
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void lock_ipi_call_lock(void)
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{
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spin_lock_irq(&call_lock);
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}
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void unlock_ipi_call_lock(void)
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{
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spin_unlock_irq(&call_lock);
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}
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/*
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* this function sends a 'generic call function' IPI to one other CPU
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* in the system.
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*
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* cpu is a standard Linux logical CPU number.
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*/
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static void
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__smp_call_function_single(int cpu, void (*func) (void *info), void *info,
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int nonatomic, int wait)
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{
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struct call_data_struct data;
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int cpus = 1;
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data.func = func;
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data.info = info;
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atomic_set(&data.started, 0);
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data.wait = wait;
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if (wait)
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atomic_set(&data.finished, 0);
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call_data = &data;
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wmb();
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/* Send a message to all other CPUs and wait for them to respond */
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send_IPI_mask(cpumask_of_cpu(cpu), CALL_FUNCTION_VECTOR);
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/* Wait for response */
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while (atomic_read(&data.started) != cpus)
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cpu_relax();
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if (!wait)
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return;
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while (atomic_read(&data.finished) != cpus)
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cpu_relax();
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}
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/*
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* smp_call_function_single - Run a function on another CPU
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* @func: The function to run. This must be fast and non-blocking.
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* @info: An arbitrary pointer to pass to the function.
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* @nonatomic: Currently unused.
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* @wait: If true, wait until function has completed on other CPUs.
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*
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* Retrurns 0 on success, else a negative status code.
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*
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* Does not return until the remote CPU is nearly ready to execute <func>
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* or is or has executed.
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*/
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int smp_call_function_single (int cpu, void (*func) (void *info), void *info,
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int nonatomic, int wait)
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{
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/* prevent preemption and reschedule on another processor */
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int me = get_cpu();
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if (cpu == me) {
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WARN_ON(1);
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put_cpu();
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return -EBUSY;
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}
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spin_lock_bh(&call_lock);
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__smp_call_function_single(cpu, func, info, nonatomic, wait);
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spin_unlock_bh(&call_lock);
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put_cpu();
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return 0;
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}
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/*
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* this function sends a 'generic call function' IPI to all other CPUs
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* in the system.
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*/
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static void __smp_call_function (void (*func) (void *info), void *info,
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int nonatomic, int wait)
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{
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struct call_data_struct data;
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int cpus = num_online_cpus()-1;
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if (!cpus)
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return;
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data.func = func;
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data.info = info;
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atomic_set(&data.started, 0);
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data.wait = wait;
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if (wait)
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atomic_set(&data.finished, 0);
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call_data = &data;
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wmb();
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/* Send a message to all other CPUs and wait for them to respond */
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send_IPI_allbutself(CALL_FUNCTION_VECTOR);
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/* Wait for response */
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while (atomic_read(&data.started) != cpus)
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cpu_relax();
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if (!wait)
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return;
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while (atomic_read(&data.finished) != cpus)
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cpu_relax();
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}
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/*
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* smp_call_function - run a function on all other CPUs.
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* @func: The function to run. This must be fast and non-blocking.
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* @info: An arbitrary pointer to pass to the function.
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* @nonatomic: currently unused.
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* @wait: If true, wait (atomically) until function has completed on other
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* CPUs.
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*
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* Returns 0 on success, else a negative status code. Does not return until
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* remote CPUs are nearly ready to execute func or are or have executed.
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*
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* You must not call this function with disabled interrupts or from a
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* hardware interrupt handler or from a bottom half handler.
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* Actually there are a few legal cases, like panic.
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*/
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int smp_call_function (void (*func) (void *info), void *info, int nonatomic,
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int wait)
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{
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spin_lock(&call_lock);
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__smp_call_function(func,info,nonatomic,wait);
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spin_unlock(&call_lock);
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return 0;
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}
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void smp_stop_cpu(void)
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{
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unsigned long flags;
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/*
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* Remove this CPU:
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*/
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cpu_clear(smp_processor_id(), cpu_online_map);
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local_irq_save(flags);
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disable_local_APIC();
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local_irq_restore(flags);
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}
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static void smp_really_stop_cpu(void *dummy)
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{
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smp_stop_cpu();
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for (;;)
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asm("hlt");
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}
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void smp_send_stop(void)
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{
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int nolock = 0;
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if (reboot_force)
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return;
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/* Don't deadlock on the call lock in panic */
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if (!spin_trylock(&call_lock)) {
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/* ignore locking because we have paniced anyways */
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nolock = 1;
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}
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__smp_call_function(smp_really_stop_cpu, NULL, 0, 0);
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if (!nolock)
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spin_unlock(&call_lock);
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local_irq_disable();
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disable_local_APIC();
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local_irq_enable();
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}
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/*
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* Reschedule call back. Nothing to do,
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* all the work is done automatically when
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* we return from the interrupt.
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*/
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asmlinkage void smp_reschedule_interrupt(void)
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{
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ack_APIC_irq();
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}
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asmlinkage void smp_call_function_interrupt(void)
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{
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void (*func) (void *info) = call_data->func;
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void *info = call_data->info;
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int wait = call_data->wait;
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ack_APIC_irq();
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/*
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* Notify initiating CPU that I've grabbed the data and am
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* about to execute the function
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*/
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mb();
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atomic_inc(&call_data->started);
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/*
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* At this point the info structure may be out of scope unless wait==1
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*/
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exit_idle();
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irq_enter();
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(*func)(info);
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irq_exit();
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if (wait) {
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mb();
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atomic_inc(&call_data->finished);
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}
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}
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int safe_smp_processor_id(void)
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{
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int apicid, i;
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if (disable_apic)
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return 0;
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apicid = hard_smp_processor_id();
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if (x86_cpu_to_apicid[apicid] == apicid)
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return apicid;
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for (i = 0; i < NR_CPUS; ++i) {
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if (x86_cpu_to_apicid[i] == apicid)
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return i;
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}
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/* No entries in x86_cpu_to_apicid? Either no MPS|ACPI,
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* or called too early. Either way, we must be CPU 0. */
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if (x86_cpu_to_apicid[0] == BAD_APICID)
|
|
return 0;
|
|
|
|
return 0; /* Should not happen */
|
|
}
|