222 lines
7.2 KiB
C
222 lines
7.2 KiB
C
/*
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* file: include/asm-blackfin/mach-bf537/irq.h
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* based on:
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* author:
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*
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* created:
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* description:
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* system mmr register map
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* rev:
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*
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* modified:
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*
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*
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* bugs: enter bugs at http://blackfin.uclinux.org/
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*
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* this program is free software; you can redistribute it and/or modify
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* it under the terms of the gnu general public license as published by
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* the free software foundation; either version 2, or (at your option)
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* any later version.
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*
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* this program is distributed in the hope that it will be useful,
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* but without any warranty; without even the implied warranty of
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* merchantability or fitness for a particular purpose. see the
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* gnu general public license for more details.
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*
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* you should have received a copy of the gnu general public license
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* along with this program; see the file copying.
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* if not, write to the free software foundation,
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* 59 temple place - suite 330, boston, ma 02111-1307, usa.
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*/
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#ifndef _BF537_IRQ_H_
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#define _BF537_IRQ_H_
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/*
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* Interrupt source definitions
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Event Source Core Event Name
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Core Emulation **
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Events (highest priority) EMU 0
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Reset RST 1
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NMI NMI 2
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Exception EVX 3
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Reserved -- 4
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Hardware Error IVHW 5
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Core Timer IVTMR 6 *
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.....
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Software Interrupt 1 IVG14 31
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Software Interrupt 2 --
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(lowest priority) IVG15 32 *
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*/
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#define SYS_IRQS 41
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#define NR_PERI_INTS 32
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/* The ABSTRACT IRQ definitions */
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/** the first seven of the following are fixed, the rest you change if you need to **/
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#define IRQ_EMU 0 /*Emulation */
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#define IRQ_RST 1 /*reset */
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#define IRQ_NMI 2 /*Non Maskable */
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#define IRQ_EVX 3 /*Exception */
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#define IRQ_UNUSED 4 /*- unused interrupt*/
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#define IRQ_HWERR 5 /*Hardware Error */
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#define IRQ_CORETMR 6 /*Core timer */
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#define IRQ_PLL_WAKEUP 7 /*PLL Wakeup Interrupt */
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#define IRQ_DMA_ERROR 8 /*DMA Error (general) */
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#define IRQ_GENERIC_ERROR 9 /*GENERIC Error Interrupt */
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#define IRQ_RTC 10 /*RTC Interrupt */
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#define IRQ_PPI 11 /*DMA0 Interrupt (PPI) */
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#define IRQ_SPORT0_RX 12 /*DMA3 Interrupt (SPORT0 RX) */
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#define IRQ_SPORT0_TX 13 /*DMA4 Interrupt (SPORT0 TX) */
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#define IRQ_SPORT1_RX 14 /*DMA5 Interrupt (SPORT1 RX) */
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#define IRQ_SPORT1_TX 15 /*DMA6 Interrupt (SPORT1 TX) */
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#define IRQ_TWI 16 /*TWI Interrupt */
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#define IRQ_SPI 17 /*DMA7 Interrupt (SPI) */
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#define IRQ_UART0_RX 18 /*DMA8 Interrupt (UART0 RX) */
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#define IRQ_UART0_TX 19 /*DMA9 Interrupt (UART0 TX) */
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#define IRQ_UART1_RX 20 /*DMA10 Interrupt (UART1 RX) */
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#define IRQ_UART1_TX 21 /*DMA11 Interrupt (UART1 TX) */
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#define IRQ_CAN_RX 22 /*CAN Receive Interrupt */
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#define IRQ_CAN_TX 23 /*CAN Transmit Interrupt */
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#define IRQ_MAC_RX 24 /*DMA1 (Ethernet RX) Interrupt */
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#define IRQ_MAC_TX 25 /*DMA2 (Ethernet TX) Interrupt */
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#define IRQ_TMR0 26 /*Timer 0 */
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#define IRQ_TMR1 27 /*Timer 1 */
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#define IRQ_TMR2 28 /*Timer 2 */
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#define IRQ_TMR3 29 /*Timer 3 */
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#define IRQ_TMR4 30 /*Timer 4 */
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#define IRQ_TMR5 31 /*Timer 5 */
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#define IRQ_TMR6 32 /*Timer 6 */
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#define IRQ_TMR7 33 /*Timer 7 */
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#define IRQ_PROG_INTA 34 /* PF Ports F&G (PF15:0) Interrupt A */
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#define IRQ_PORTG_INTB 35 /* PF Port G (PF15:0) Interrupt B */
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#define IRQ_MEM_DMA0 36 /*(Memory DMA Stream 0) */
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#define IRQ_MEM_DMA1 37 /*(Memory DMA Stream 1) */
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#define IRQ_PROG_INTB 38 /* PF Ports F (PF15:0) Interrupt B */
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#define IRQ_WATCH 38 /*Watch Dog Timer */
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#define IRQ_SW_INT1 40 /*Software Int 1 */
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#define IRQ_SW_INT2 41 /*Software Int 2 (reserved for SYSCALL) */
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#define IRQ_PPI_ERROR 42 /*PPI Error Interrupt */
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#define IRQ_CAN_ERROR 43 /*CAN Error Interrupt */
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#define IRQ_MAC_ERROR 44 /*PPI Error Interrupt */
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#define IRQ_SPORT0_ERROR 45 /*SPORT0 Error Interrupt */
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#define IRQ_SPORT1_ERROR 46 /*SPORT1 Error Interrupt */
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#define IRQ_SPI_ERROR 47 /*SPI Error Interrupt */
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#define IRQ_UART0_ERROR 48 /*UART Error Interrupt */
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#define IRQ_UART1_ERROR 49 /*UART Error Interrupt */
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#define IRQ_PF0 50
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#define IRQ_PF1 51
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#define IRQ_PF2 52
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#define IRQ_PF3 53
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#define IRQ_PF4 54
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#define IRQ_PF5 55
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#define IRQ_PF6 56
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#define IRQ_PF7 57
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#define IRQ_PF8 58
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#define IRQ_PF9 59
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#define IRQ_PF10 60
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#define IRQ_PF11 61
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#define IRQ_PF12 62
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#define IRQ_PF13 63
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#define IRQ_PF14 64
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#define IRQ_PF15 65
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#define IRQ_PG0 66
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#define IRQ_PG1 67
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#define IRQ_PG2 68
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#define IRQ_PG3 69
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#define IRQ_PG4 70
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#define IRQ_PG5 71
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#define IRQ_PG6 72
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#define IRQ_PG7 73
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#define IRQ_PG8 74
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#define IRQ_PG9 75
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#define IRQ_PG10 76
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#define IRQ_PG11 77
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#define IRQ_PG12 78
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#define IRQ_PG13 79
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#define IRQ_PG14 80
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#define IRQ_PG15 81
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#define IRQ_PH0 82
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#define IRQ_PH1 83
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#define IRQ_PH2 84
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#define IRQ_PH3 85
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#define IRQ_PH4 86
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#define IRQ_PH5 87
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#define IRQ_PH6 88
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#define IRQ_PH7 89
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#define IRQ_PH8 90
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#define IRQ_PH9 91
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#define IRQ_PH10 92
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#define IRQ_PH11 93
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#define IRQ_PH12 94
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#define IRQ_PH13 95
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#define IRQ_PH14 96
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#define IRQ_PH15 97
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#define GPIO_IRQ_BASE IRQ_PF0
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#ifdef CONFIG_IRQCHIP_DEMUX_GPIO
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#define NR_IRQS (IRQ_PH15+1)
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#else
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#define NR_IRQS (IRQ_UART1_ERROR+1)
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#endif
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#define IVG7 7
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#define IVG8 8
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#define IVG9 9
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#define IVG10 10
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#define IVG11 11
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#define IVG12 12
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#define IVG13 13
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#define IVG14 14
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#define IVG15 15
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/* IAR0 BIT FIELDS*/
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#define IRQ_PLL_WAKEUP_POS 0
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#define IRQ_DMA_ERROR_POS 4
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#define IRQ_ERROR_POS 8
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#define IRQ_RTC_POS 12
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#define IRQ_PPI_POS 16
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#define IRQ_SPORT0_RX_POS 20
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#define IRQ_SPORT0_TX_POS 24
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#define IRQ_SPORT1_RX_POS 28
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/* IAR1 BIT FIELDS*/
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#define IRQ_SPORT1_TX_POS 0
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#define IRQ_TWI_POS 4
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#define IRQ_SPI_POS 8
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#define IRQ_UART0_RX_POS 12
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#define IRQ_UART0_TX_POS 16
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#define IRQ_UART1_RX_POS 20
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#define IRQ_UART1_TX_POS 24
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#define IRQ_CAN_RX_POS 28
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/* IAR2 BIT FIELDS*/
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#define IRQ_CAN_TX_POS 0
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#define IRQ_MAC_RX_POS 4
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#define IRQ_MAC_TX_POS 8
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#define IRQ_TMR0_POS 12
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#define IRQ_TMR1_POS 16
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#define IRQ_TMR2_POS 20
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#define IRQ_TMR3_POS 24
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#define IRQ_TMR4_POS 28
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/* IAR3 BIT FIELDS*/
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#define IRQ_TMR5_POS 0
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#define IRQ_TMR6_POS 4
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#define IRQ_TMR7_POS 8
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#define IRQ_PROG_INTA_POS 12
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#define IRQ_PORTG_INTB_POS 16
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#define IRQ_MEM_DMA0_POS 20
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#define IRQ_MEM_DMA1_POS 24
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#define IRQ_WATCH_POS 28
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#endif /* _BF537_IRQ_H_ */
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