256 lines
8.0 KiB
C
256 lines
8.0 KiB
C
/*
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*
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* BRIEF MODULE DESCRIPTION
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* Alchemy Db1x00 board setup.
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*
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* Copyright 2000, 2008 MontaVista Software Inc.
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* Author: MontaVista Software, Inc. <source@mvista.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
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* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
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* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <linux/gpio.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/pm.h>
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#include <asm/mach-au1x00/au1000.h>
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#include <asm/mach-au1x00/au1xxx_eth.h>
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#include <asm/mach-db1x00/db1x00.h>
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#include <asm/mach-db1x00/bcsr.h>
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#include <asm/reboot.h>
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#include <prom.h>
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#ifdef CONFIG_MIPS_DB1500
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char irq_tab_alchemy[][5] __initdata = {
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[12] = { -1, AU1500_PCI_INTA, 0xff, 0xff, 0xff }, /* IDSEL 12 - HPT371 */
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[13] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, AU1500_PCI_INTC, AU1500_PCI_INTD }, /* IDSEL 13 - PCI slot */
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};
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#endif
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#ifdef CONFIG_MIPS_DB1550
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char irq_tab_alchemy[][5] __initdata = {
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[11] = { -1, AU1550_PCI_INTC, 0xff, 0xff, 0xff }, /* IDSEL 11 - on-board HPT371 */
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[12] = { -1, AU1550_PCI_INTB, AU1550_PCI_INTC, AU1550_PCI_INTD, AU1550_PCI_INTA }, /* IDSEL 12 - PCI slot 2 (left) */
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[13] = { -1, AU1550_PCI_INTA, AU1550_PCI_INTB, AU1550_PCI_INTC, AU1550_PCI_INTD }, /* IDSEL 13 - PCI slot 1 (right) */
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};
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#endif
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#ifdef CONFIG_MIPS_BOSPORUS
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char irq_tab_alchemy[][5] __initdata = {
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[11] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, 0xff, 0xff }, /* IDSEL 11 - miniPCI */
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[12] = { -1, AU1500_PCI_INTA, 0xff, 0xff, 0xff }, /* IDSEL 12 - SN1741 */
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[13] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, AU1500_PCI_INTC, AU1500_PCI_INTD }, /* IDSEL 13 - PCI slot */
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};
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/*
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* Micrel/Kendin 5 port switch attached to MAC0,
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* MAC0 is associated with PHY address 5 (== WAN port)
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* MAC1 is not associated with any PHY, since it's connected directly
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* to the switch.
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* no interrupts are used
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*/
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static struct au1000_eth_platform_data eth0_pdata = {
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.phy_static_config = 1,
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.phy_addr = 5,
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};
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static void bosporus_power_off(void)
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{
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while (1)
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asm volatile (".set mips3 ; wait ; .set mips0");
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}
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const char *get_system_type(void)
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{
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return "Alchemy Bosporus Gateway Reference";
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}
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#endif
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#ifdef CONFIG_MIPS_MIRAGE
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char irq_tab_alchemy[][5] __initdata = {
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[11] = { -1, AU1500_PCI_INTD, 0xff, 0xff, 0xff }, /* IDSEL 11 - SMI VGX */
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[12] = { -1, 0xff, 0xff, AU1500_PCI_INTC, 0xff }, /* IDSEL 12 - PNX1300 */
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[13] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, 0xff, 0xff }, /* IDSEL 13 - miniPCI */
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};
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static void mirage_power_off(void)
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{
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alchemy_gpio_direction_output(210, 1);
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}
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const char *get_system_type(void)
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{
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return "Alchemy Mirage";
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}
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#endif
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#if defined(CONFIG_MIPS_BOSPORUS) || defined(CONFIG_MIPS_MIRAGE)
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static void mips_softreset(void)
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{
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asm volatile ("jr\t%0" : : "r"(0xbfc00000));
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}
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#else
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const char *get_system_type(void)
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{
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return "Alchemy Db1x00";
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}
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#endif
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void __init board_setup(void)
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{
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unsigned long bcsr1, bcsr2;
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bcsr1 = DB1000_BCSR_PHYS_ADDR;
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bcsr2 = DB1000_BCSR_PHYS_ADDR + DB1000_BCSR_HEXLED_OFS;
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#ifdef CONFIG_MIPS_DB1000
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printk(KERN_INFO "AMD Alchemy Au1000/Db1000 Board\n");
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#endif
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#ifdef CONFIG_MIPS_DB1500
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printk(KERN_INFO "AMD Alchemy Au1500/Db1500 Board\n");
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#endif
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#ifdef CONFIG_MIPS_DB1100
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printk(KERN_INFO "AMD Alchemy Au1100/Db1100 Board\n");
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#endif
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#ifdef CONFIG_MIPS_BOSPORUS
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au1xxx_override_eth_cfg(0, ð0_pdata);
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printk(KERN_INFO "AMD Alchemy Bosporus Board\n");
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#endif
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#ifdef CONFIG_MIPS_MIRAGE
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printk(KERN_INFO "AMD Alchemy Mirage Board\n");
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#endif
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#ifdef CONFIG_MIPS_DB1550
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printk(KERN_INFO "AMD Alchemy Au1550/Db1550 Board\n");
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bcsr1 = DB1550_BCSR_PHYS_ADDR;
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bcsr2 = DB1550_BCSR_PHYS_ADDR + DB1550_BCSR_HEXLED_OFS;
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#endif
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/* initialize board register space */
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bcsr_init(bcsr1, bcsr2);
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/* Not valid for Au1550 */
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#if defined(CONFIG_IRDA) && \
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(defined(CONFIG_SOC_AU1000) || defined(CONFIG_SOC_AU1100))
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{
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u32 pin_func;
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/* Set IRFIRSEL instead of GPIO15 */
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pin_func = au_readl(SYS_PINFUNC) | SYS_PF_IRF;
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au_writel(pin_func, SYS_PINFUNC);
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/* Power off until the driver is in use */
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bcsr_mod(BCSR_RESETS, BCSR_RESETS_IRDA_MODE_MASK,
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BCSR_RESETS_IRDA_MODE_OFF);
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}
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#endif
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bcsr_write(BCSR_PCMCIA, 0); /* turn off PCMCIA power */
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/* Enable GPIO[31:0] inputs */
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alchemy_gpio1_input_enable();
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#ifdef CONFIG_MIPS_MIRAGE
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{
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u32 pin_func;
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/* GPIO[20] is output */
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alchemy_gpio_direction_output(20, 0);
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/* Set GPIO[210:208] instead of SSI_0 */
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pin_func = au_readl(SYS_PINFUNC) | SYS_PF_S0;
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/* Set GPIO[215:211] for LEDs */
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pin_func |= 5 << 2;
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/* Set GPIO[214:213] for more LEDs */
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pin_func |= 5 << 12;
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/* Set GPIO[207:200] instead of PCMCIA/LCD */
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pin_func |= SYS_PF_LCD | SYS_PF_PC;
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au_writel(pin_func, SYS_PINFUNC);
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/*
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* Enable speaker amplifier. This should
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* be part of the audio driver.
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*/
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alchemy_gpio_direction_output(209, 1);
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pm_power_off = mirage_power_off;
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_machine_halt = mirage_power_off;
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_machine_restart = (void(*)(char *))mips_softreset;
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}
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#endif
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#ifdef CONFIG_MIPS_BOSPORUS
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pm_power_off = bosporus_power_off;
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_machine_halt = bosporus_power_off;
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_machine_restart = (void(*)(char *))mips_softreset;
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#endif
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au_sync();
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}
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static int __init db1x00_init_irq(void)
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{
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#if defined(CONFIG_MIPS_MIRAGE)
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irq_set_irq_type(AU1500_GPIO7_INT, IRQF_TRIGGER_RISING); /* TS pendown */
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#elif defined(CONFIG_MIPS_DB1550)
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irq_set_irq_type(AU1550_GPIO0_INT, IRQF_TRIGGER_LOW); /* CD0# */
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irq_set_irq_type(AU1550_GPIO1_INT, IRQF_TRIGGER_LOW); /* CD1# */
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irq_set_irq_type(AU1550_GPIO3_INT, IRQF_TRIGGER_LOW); /* CARD0# */
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irq_set_irq_type(AU1550_GPIO5_INT, IRQF_TRIGGER_LOW); /* CARD1# */
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irq_set_irq_type(AU1550_GPIO21_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */
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irq_set_irq_type(AU1550_GPIO22_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */
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#elif defined(CONFIG_MIPS_DB1500)
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irq_set_irq_type(AU1500_GPIO0_INT, IRQF_TRIGGER_LOW); /* CD0# */
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irq_set_irq_type(AU1500_GPIO3_INT, IRQF_TRIGGER_LOW); /* CD1# */
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irq_set_irq_type(AU1500_GPIO2_INT, IRQF_TRIGGER_LOW); /* CARD0# */
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irq_set_irq_type(AU1500_GPIO5_INT, IRQF_TRIGGER_LOW); /* CARD1# */
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irq_set_irq_type(AU1500_GPIO1_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */
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irq_set_irq_type(AU1500_GPIO4_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */
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#elif defined(CONFIG_MIPS_DB1100)
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irq_set_irq_type(AU1100_GPIO0_INT, IRQF_TRIGGER_LOW); /* CD0# */
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irq_set_irq_type(AU1100_GPIO3_INT, IRQF_TRIGGER_LOW); /* CD1# */
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irq_set_irq_type(AU1100_GPIO2_INT, IRQF_TRIGGER_LOW); /* CARD0# */
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irq_set_irq_type(AU1100_GPIO5_INT, IRQF_TRIGGER_LOW); /* CARD1# */
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irq_set_irq_type(AU1100_GPIO1_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */
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irq_set_irq_type(AU1100_GPIO4_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */
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#elif defined(CONFIG_MIPS_DB1000)
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irq_set_irq_type(AU1000_GPIO0_INT, IRQF_TRIGGER_LOW); /* CD0# */
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irq_set_irq_type(AU1000_GPIO3_INT, IRQF_TRIGGER_LOW); /* CD1# */
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irq_set_irq_type(AU1000_GPIO2_INT, IRQF_TRIGGER_LOW); /* CARD0# */
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irq_set_irq_type(AU1000_GPIO5_INT, IRQF_TRIGGER_LOW); /* CARD1# */
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irq_set_irq_type(AU1000_GPIO1_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */
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irq_set_irq_type(AU1000_GPIO4_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */
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#endif
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return 0;
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}
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arch_initcall(db1x00_init_irq);
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