129 lines
3.3 KiB
C
129 lines
3.3 KiB
C
/*
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* Copyright 2010 Tilera Corporation. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation, version 2.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
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* NON INFRINGEMENT. See the GNU General Public License for
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* more details.
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*/
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#ifndef _ASM_TILE_PCI_H
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#define _ASM_TILE_PCI_H
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#include <asm/pci-bridge.h>
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/*
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* The hypervisor maps the entirety of CPA-space as bus addresses, so
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* bus addresses are physical addresses. The networking and block
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* device layers use this boolean for bounce buffer decisions.
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*/
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#define PCI_DMA_BUS_IS_PHYS 1
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struct pci_controller *pci_bus_to_hose(int bus);
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unsigned char __init common_swizzle(struct pci_dev *dev, unsigned char *pinp);
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int __init tile_pci_init(void);
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void pci_iounmap(struct pci_dev *dev, void __iomem *addr);
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void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max);
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void __devinit pcibios_fixup_bus(struct pci_bus *bus);
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int __devinit _tile_cfg_read(struct pci_controller *hose,
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int bus,
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int slot,
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int function,
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int offset,
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int size,
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u32 *val);
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int __devinit _tile_cfg_write(struct pci_controller *hose,
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int bus,
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int slot,
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int function,
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int offset,
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int size,
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u32 val);
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/*
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* These are used to to config reads and writes in the early stages of
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* setup before the driver infrastructure has been set up enough to be
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* able to do config reads and writes.
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*/
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#define early_cfg_read(where, size, value) \
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_tile_cfg_read(controller, \
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current_bus, \
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pci_slot, \
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pci_fn, \
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where, \
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size, \
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value)
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#define early_cfg_write(where, size, value) \
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_tile_cfg_write(controller, \
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current_bus, \
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pci_slot, \
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pci_fn, \
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where, \
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size, \
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value)
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#define PCICFG_BYTE 1
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#define PCICFG_WORD 2
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#define PCICFG_DWORD 4
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#define TILE_NUM_PCIE 2
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#define pci_domain_nr(bus) (((struct pci_controller *)(bus)->sysdata)->index)
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/*
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* This decides whether to display the domain number in /proc.
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*/
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static inline int pci_proc_domain(struct pci_bus *bus)
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{
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return 1;
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}
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/*
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* I/O space is currently not supported.
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*/
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#define TILE_PCIE_LOWER_IO 0x0
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#define TILE_PCIE_UPPER_IO 0x10000
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#define TILE_PCIE_PCIE_IO_SIZE 0x0000FFFF
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#define _PAGE_NO_CACHE 0
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#define _PAGE_GUARDED 0
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#define pcibios_assign_all_busses() pci_assign_all_buses
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extern int pci_assign_all_buses;
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static inline void pcibios_set_master(struct pci_dev *dev)
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{
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/* No special bus mastering setup handling */
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}
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#define PCIBIOS_MIN_MEM 0
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#define PCIBIOS_MIN_IO TILE_PCIE_LOWER_IO
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/*
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* This flag tells if the platform is TILEmpower that needs
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* special configuration for the PLX switch chip.
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*/
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extern int blade_pci;
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/* implement the pci_ DMA API in terms of the generic device dma_ one */
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#include <asm-generic/pci-dma-compat.h>
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/* generic pci stuff */
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#include <asm-generic/pci.h>
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/* Use any cpu for PCI. */
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#define cpumask_of_pcibus(bus) cpu_online_mask
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#endif /* _ASM_TILE_PCI_H */
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