217 lines
9.4 KiB
C
217 lines
9.4 KiB
C
/*
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* DO NOT EDIT THIS FILE
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* This file is under version control at
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* svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/
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* and can be replaced with that version at any time
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* DO NOT EDIT THIS FILE
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*
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* Copyright 2004-2009 Analog Devices Inc.
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* Licensed under the ADI BSD license.
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* https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
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*/
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/* This file should be up to date with:
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* - Revision D, 09/18/2008; ADSP-BF534/ADSP-BF536/ADSP-BF537 Blackfin Processor Anomaly List
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*/
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#ifndef _MACH_ANOMALY_H_
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#define _MACH_ANOMALY_H_
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/* We do not support 0.1 silicon - sorry */
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#if __SILICON_REVISION__ < 2
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# error will not work on BF537 silicon version 0.0 or 0.1
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#endif
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#if defined(__ADSPBF534__)
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# define ANOMALY_BF534 1
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#else
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# define ANOMALY_BF534 0
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#endif
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#if defined(__ADSPBF536__)
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# define ANOMALY_BF536 1
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#else
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# define ANOMALY_BF536 0
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#endif
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#if defined(__ADSPBF537__)
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# define ANOMALY_BF537 1
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#else
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# define ANOMALY_BF537 0
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#endif
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/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
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#define ANOMALY_05000074 (1)
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/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
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#define ANOMALY_05000119 (1)
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/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
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#define ANOMALY_05000122 (1)
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/* Killed 32-Bit MMR Write Leads to Next System MMR Access Thinking It Should Be 32-Bit */
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#define ANOMALY_05000157 (__SILICON_REVISION__ < 2)
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/* PPI_DELAY Not Functional in PPI Modes with 0 Frame Syncs */
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#define ANOMALY_05000180 (1)
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/* Instruction Cache Is Not Functional */
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#define ANOMALY_05000237 (__SILICON_REVISION__ < 2)
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/* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */
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#define ANOMALY_05000244 (__SILICON_REVISION__ < 3)
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/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
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#define ANOMALY_05000245 (1)
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/* Buffered CLKIN Output Is Disabled by Default */
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#define ANOMALY_05000247 (1)
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/* Incorrect Bit Shift of Data Word in Multichannel (TDM) Mode in Certain Conditions */
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#define ANOMALY_05000250 (__SILICON_REVISION__ < 3)
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/* EMAC TX DMA Error After an Early Frame Abort */
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#define ANOMALY_05000252 (__SILICON_REVISION__ < 3)
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/* Maximum External Clock Speed for Timers */
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#define ANOMALY_05000253 (__SILICON_REVISION__ < 3)
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/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */
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#define ANOMALY_05000254 (__SILICON_REVISION__ > 2)
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/* Entering Hibernate State with RTC Seconds Interrupt Not Functional */
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#define ANOMALY_05000255 (__SILICON_REVISION__ < 3)
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/* EMAC MDIO Input Latched on Wrong MDC Edge */
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#define ANOMALY_05000256 (__SILICON_REVISION__ < 3)
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/* Interrupt/Exception During Short Hardware Loop May Cause Bad Instruction Fetches */
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#define ANOMALY_05000257 (__SILICON_REVISION__ < 3)
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/* Instruction Cache Is Corrupted When Bits 9 and 12 of the ICPLB Data Registers Differ */
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#define ANOMALY_05000258 (((ANOMALY_BF536 || ANOMALY_BF537) && __SILICON_REVISION__ == 1) || __SILICON_REVISION__ == 2)
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/* ICPLB_STATUS MMR Register May Be Corrupted */
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#define ANOMALY_05000260 (__SILICON_REVISION__ == 2)
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/* DCPLB_FAULT_ADDR MMR Register May Be Corrupted */
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#define ANOMALY_05000261 (__SILICON_REVISION__ < 3)
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/* Stores To Data Cache May Be Lost */
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#define ANOMALY_05000262 (__SILICON_REVISION__ < 3)
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/* Hardware Loop Corrupted When Taking an ICPLB Exception */
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#define ANOMALY_05000263 (__SILICON_REVISION__ == 2)
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/* CSYNC/SSYNC/IDLE Causes Infinite Stall in Penultimate Instruction in Hardware Loop */
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#define ANOMALY_05000264 (__SILICON_REVISION__ < 3)
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/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
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#define ANOMALY_05000265 (1)
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/* Memory DMA Error when Peripheral DMA Is Running with Non-Zero DEB_TRAFFIC_PERIOD */
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#define ANOMALY_05000268 (__SILICON_REVISION__ < 3)
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/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */
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#define ANOMALY_05000270 (__SILICON_REVISION__ < 3)
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/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
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#define ANOMALY_05000272 (1)
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/* Writes to Synchronous SDRAM Memory May Be Lost */
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#define ANOMALY_05000273 (__SILICON_REVISION__ < 3)
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/* Writes to an I/O Data Register One SCLK Cycle after an Edge Is Detected May Clear Interrupt */
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#define ANOMALY_05000277 (__SILICON_REVISION__ < 3)
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/* Disabling Peripherals with DMA Running May Cause DMA System Instability */
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#define ANOMALY_05000278 (((ANOMALY_BF536 || ANOMALY_BF537) && __SILICON_REVISION__ < 3) || (ANOMALY_BF534 && __SILICON_REVISION__ < 2))
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/* SPI Master Boot Mode Does Not Work Well with Atmel Data Flash Devices */
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#define ANOMALY_05000280 (1)
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/* False Hardware Error Exception when ISR Context Is Not Restored */
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#define ANOMALY_05000281 (__SILICON_REVISION__ < 3)
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/* Memory DMA Corruption with 32-Bit Data and Traffic Control */
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#define ANOMALY_05000282 (__SILICON_REVISION__ < 3)
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/* System MMR Write Is Stalled Indefinitely when Killed in a Particular Stage */
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#define ANOMALY_05000283 (__SILICON_REVISION__ < 3)
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/* TXDWA Bit in EMAC_SYSCTL Register Is Not Functional */
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#define ANOMALY_05000285 (__SILICON_REVISION__ < 3)
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/* SPORTs May Receive Bad Data If FIFOs Fill Up */
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#define ANOMALY_05000288 (__SILICON_REVISION__ < 3)
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/* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */
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#define ANOMALY_05000301 (1)
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/* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */
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#define ANOMALY_05000304 (__SILICON_REVISION__ < 3)
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/* SPORT_HYS Bit in PLL_CTL Register Is Not Functional */
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#define ANOMALY_05000305 (__SILICON_REVISION__ < 3)
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/* SCKELOW Bit Does Not Maintain State Through Hibernate */
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#define ANOMALY_05000307 (__SILICON_REVISION__ < 3)
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/* Writing UART_THR While UART Clock Is Disabled Sends Erroneous Start Bit */
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#define ANOMALY_05000309 (__SILICON_REVISION__ < 3)
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/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
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#define ANOMALY_05000310 (1)
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/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
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#define ANOMALY_05000312 (1)
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/* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */
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#define ANOMALY_05000313 (1)
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/* Killed System MMR Write Completes Erroneously on Next System MMR Access */
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#define ANOMALY_05000315 (__SILICON_REVISION__ < 3)
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/* EMAC RMII Mode: Collisions Occur in Full Duplex Mode */
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#define ANOMALY_05000316 (__SILICON_REVISION__ < 3)
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/* EMAC RMII Mode: TX Frames in Half Duplex Fail with Status "No Carrier" */
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#define ANOMALY_05000321 (__SILICON_REVISION__ < 3)
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/* EMAC RMII Mode at 10-Base-T Speed: RX Frames Not Received Properly */
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#define ANOMALY_05000322 (1)
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/* Ethernet MAC MDIO Reads Do Not Meet IEEE Specification */
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#define ANOMALY_05000341 (__SILICON_REVISION__ >= 3)
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/* UART Gets Disabled after UART Boot */
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#define ANOMALY_05000350 (__SILICON_REVISION__ >= 3)
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/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */
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#define ANOMALY_05000355 (1)
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/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
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#define ANOMALY_05000357 (1)
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/* DMAs that Go Urgent during Tight Core Writes to External Memory Are Blocked */
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#define ANOMALY_05000359 (1)
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/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
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#define ANOMALY_05000366 (1)
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/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
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#define ANOMALY_05000371 (1)
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/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */
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#define ANOMALY_05000402 (__SILICON_REVISION__ == 2)
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/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
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#define ANOMALY_05000403 (1)
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/* Speculative Fetches Can Cause Undesired External FIFO Operations */
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#define ANOMALY_05000416 (1)
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/* Multichannel SPORT Channel Misalignment Under Specific Configuration */
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#define ANOMALY_05000425 (1)
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/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
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#define ANOMALY_05000426 (1)
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/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
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#define ANOMALY_05000443 (1)
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/* False Hardware Error when RETI Points to Invalid Memory */
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#define ANOMALY_05000461 (1)
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/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */
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#define ANOMALY_05000473 (1)
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/* TESTSET Instruction Cannot Be Interrupted */
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#define ANOMALY_05000477 (1)
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/* Anomalies that don't exist on this proc */
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#define ANOMALY_05000099 (0)
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#define ANOMALY_05000120 (0)
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#define ANOMALY_05000125 (0)
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#define ANOMALY_05000149 (0)
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#define ANOMALY_05000158 (0)
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#define ANOMALY_05000171 (0)
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#define ANOMALY_05000179 (0)
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#define ANOMALY_05000182 (0)
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#define ANOMALY_05000183 (0)
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#define ANOMALY_05000189 (0)
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#define ANOMALY_05000198 (0)
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#define ANOMALY_05000202 (0)
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#define ANOMALY_05000215 (0)
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#define ANOMALY_05000220 (0)
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#define ANOMALY_05000227 (0)
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#define ANOMALY_05000230 (0)
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#define ANOMALY_05000231 (0)
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#define ANOMALY_05000233 (0)
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#define ANOMALY_05000234 (0)
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#define ANOMALY_05000242 (0)
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#define ANOMALY_05000248 (0)
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#define ANOMALY_05000266 (0)
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#define ANOMALY_05000274 (0)
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#define ANOMALY_05000287 (0)
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#define ANOMALY_05000311 (0)
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#define ANOMALY_05000323 (0)
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#define ANOMALY_05000353 (1)
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#define ANOMALY_05000362 (1)
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#define ANOMALY_05000363 (0)
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#define ANOMALY_05000364 (0)
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#define ANOMALY_05000380 (0)
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#define ANOMALY_05000386 (1)
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#define ANOMALY_05000389 (0)
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#define ANOMALY_05000400 (0)
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#define ANOMALY_05000412 (0)
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#define ANOMALY_05000430 (0)
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#define ANOMALY_05000432 (0)
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#define ANOMALY_05000435 (0)
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#define ANOMALY_05000447 (0)
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#define ANOMALY_05000448 (0)
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#define ANOMALY_05000456 (0)
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#define ANOMALY_05000450 (0)
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#define ANOMALY_05000465 (0)
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#define ANOMALY_05000467 (0)
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#define ANOMALY_05000474 (0)
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#define ANOMALY_05000475 (0)
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#endif
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