94 lines
2.3 KiB
C
94 lines
2.3 KiB
C
/*
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* intc-1.c
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*
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* (C) Copyright 2009, Greg Ungerer <gerg@snapgear.com>
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file COPYING in the main directory of this archive
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* for more details.
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*/
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#include <linux/types.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/io.h>
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#include <asm/coldfire.h>
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#include <asm/mcfsim.h>
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#include <asm/traps.h>
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/*
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* Each vector needs a unique priority and level asscoiated with it.
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* We don't really care so much what they are, we don't rely on the
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* tranditional priority interrupt scheme of the m68k/ColdFire.
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*/
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static u8 intc_intpri = 0x36;
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static void intc_irq_mask(unsigned int irq)
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{
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if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECBASE + 128)) {
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unsigned long imraddr;
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u32 val, imrbit;
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irq -= MCFINT_VECBASE;
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imraddr = MCF_IPSBAR;
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imraddr += (irq & 0x40) ? MCFICM_INTC1 : MCFICM_INTC0;
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imraddr += (irq & 0x20) ? MCFINTC_IMRH : MCFINTC_IMRL;
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imrbit = 0x1 << (irq & 0x1f);
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val = __raw_readl(imraddr);
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__raw_writel(val | imrbit, imraddr);
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}
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}
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static void intc_irq_unmask(unsigned int irq)
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{
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if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECBASE + 128)) {
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unsigned long intaddr, imraddr, icraddr;
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u32 val, imrbit;
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irq -= MCFINT_VECBASE;
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intaddr = MCF_IPSBAR;
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intaddr += (irq & 0x40) ? MCFICM_INTC1 : MCFICM_INTC0;
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imraddr = intaddr + ((irq & 0x20) ? MCFINTC_IMRH : MCFINTC_IMRL);
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icraddr = intaddr + MCFINTC_ICR0 + (irq & 0x3f);
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imrbit = 0x1 << (irq & 0x1f);
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/* Don't set the "maskall" bit! */
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if ((irq & 0x20) == 0)
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imrbit |= 0x1;
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if (__raw_readb(icraddr) == 0)
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__raw_writeb(intc_intpri--, icraddr);
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val = __raw_readl(imraddr);
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__raw_writel(val & ~imrbit, imraddr);
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}
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}
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static struct irq_chip intc_irq_chip = {
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.name = "CF-INTC",
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.mask = intc_irq_mask,
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.unmask = intc_irq_unmask,
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};
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void __init init_IRQ(void)
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{
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int irq;
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init_vectors();
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/* Mask all interrupt sources */
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__raw_writel(0x1, MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_IMRL);
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__raw_writel(0x1, MCF_IPSBAR + MCFICM_INTC1 + MCFINTC_IMRL);
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for (irq = 0; (irq < NR_IRQS); irq++) {
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irq_desc[irq].status = IRQ_DISABLED;
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irq_desc[irq].action = NULL;
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irq_desc[irq].depth = 1;
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irq_desc[irq].chip = &intc_irq_chip;
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}
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}
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