519 lines
14 KiB
C
519 lines
14 KiB
C
/*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, version 2, as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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*
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* Copyright IBM Corp. 2007
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*
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* Authors: Hollis Blanchard <hollisb@us.ibm.com>
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*/
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#include <linux/types.h>
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#include <linux/string.h>
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#include <linux/kvm.h>
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#include <linux/kvm_host.h>
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#include <linux/highmem.h>
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#include <asm/tlbflush.h>
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#include <asm/mmu-44x.h>
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#include <asm/kvm_ppc.h>
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#include <asm/kvm_44x.h>
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#include "timing.h"
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#include "44x_tlb.h"
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#include "trace.h"
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#ifndef PPC44x_TLBE_SIZE
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#define PPC44x_TLBE_SIZE PPC44x_TLB_4K
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#endif
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#define PAGE_SIZE_4K (1<<12)
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#define PAGE_MASK_4K (~(PAGE_SIZE_4K - 1))
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#define PPC44x_TLB_UATTR_MASK \
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(PPC44x_TLB_U0|PPC44x_TLB_U1|PPC44x_TLB_U2|PPC44x_TLB_U3)
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#define PPC44x_TLB_USER_PERM_MASK (PPC44x_TLB_UX|PPC44x_TLB_UR|PPC44x_TLB_UW)
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#define PPC44x_TLB_SUPER_PERM_MASK (PPC44x_TLB_SX|PPC44x_TLB_SR|PPC44x_TLB_SW)
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#ifdef DEBUG
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void kvmppc_dump_tlbs(struct kvm_vcpu *vcpu)
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{
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struct kvmppc_44x_tlbe *tlbe;
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int i;
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printk("vcpu %d TLB dump:\n", vcpu->vcpu_id);
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printk("| %2s | %3s | %8s | %8s | %8s |\n",
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"nr", "tid", "word0", "word1", "word2");
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for (i = 0; i < ARRAY_SIZE(vcpu_44x->guest_tlb); i++) {
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tlbe = &vcpu_44x->guest_tlb[i];
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if (tlbe->word0 & PPC44x_TLB_VALID)
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printk(" G%2d | %02X | %08X | %08X | %08X |\n",
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i, tlbe->tid, tlbe->word0, tlbe->word1,
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tlbe->word2);
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}
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}
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#endif
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static inline void kvmppc_44x_tlbie(unsigned int index)
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{
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/* 0 <= index < 64, so the V bit is clear and we can use the index as
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* word0. */
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asm volatile(
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"tlbwe %[index], %[index], 0\n"
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:
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: [index] "r"(index)
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);
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}
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static inline void kvmppc_44x_tlbre(unsigned int index,
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struct kvmppc_44x_tlbe *tlbe)
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{
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asm volatile(
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"tlbre %[word0], %[index], 0\n"
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"mfspr %[tid], %[sprn_mmucr]\n"
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"andi. %[tid], %[tid], 0xff\n"
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"tlbre %[word1], %[index], 1\n"
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"tlbre %[word2], %[index], 2\n"
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: [word0] "=r"(tlbe->word0),
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[word1] "=r"(tlbe->word1),
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[word2] "=r"(tlbe->word2),
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[tid] "=r"(tlbe->tid)
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: [index] "r"(index),
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[sprn_mmucr] "i"(SPRN_MMUCR)
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: "cc"
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);
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}
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static inline void kvmppc_44x_tlbwe(unsigned int index,
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struct kvmppc_44x_tlbe *stlbe)
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{
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unsigned long tmp;
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asm volatile(
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"mfspr %[tmp], %[sprn_mmucr]\n"
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"rlwimi %[tmp], %[tid], 0, 0xff\n"
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"mtspr %[sprn_mmucr], %[tmp]\n"
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"tlbwe %[word0], %[index], 0\n"
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"tlbwe %[word1], %[index], 1\n"
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"tlbwe %[word2], %[index], 2\n"
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: [tmp] "=&r"(tmp)
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: [word0] "r"(stlbe->word0),
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[word1] "r"(stlbe->word1),
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[word2] "r"(stlbe->word2),
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[tid] "r"(stlbe->tid),
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[index] "r"(index),
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[sprn_mmucr] "i"(SPRN_MMUCR)
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);
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}
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static u32 kvmppc_44x_tlb_shadow_attrib(u32 attrib, int usermode)
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{
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/* We only care about the guest's permission and user bits. */
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attrib &= PPC44x_TLB_PERM_MASK|PPC44x_TLB_UATTR_MASK;
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if (!usermode) {
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/* Guest is in supervisor mode, so we need to translate guest
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* supervisor permissions into user permissions. */
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attrib &= ~PPC44x_TLB_USER_PERM_MASK;
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attrib |= (attrib & PPC44x_TLB_SUPER_PERM_MASK) << 3;
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}
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/* Make sure host can always access this memory. */
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attrib |= PPC44x_TLB_SX|PPC44x_TLB_SR|PPC44x_TLB_SW;
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/* WIMGE = 0b00100 */
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attrib |= PPC44x_TLB_M;
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return attrib;
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}
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/* Load shadow TLB back into hardware. */
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void kvmppc_44x_tlb_load(struct kvm_vcpu *vcpu)
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{
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struct kvmppc_vcpu_44x *vcpu_44x = to_44x(vcpu);
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int i;
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for (i = 0; i <= tlb_44x_hwater; i++) {
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struct kvmppc_44x_tlbe *stlbe = &vcpu_44x->shadow_tlb[i];
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if (get_tlb_v(stlbe) && get_tlb_ts(stlbe))
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kvmppc_44x_tlbwe(i, stlbe);
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}
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}
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static void kvmppc_44x_tlbe_set_modified(struct kvmppc_vcpu_44x *vcpu_44x,
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unsigned int i)
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{
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vcpu_44x->shadow_tlb_mod[i] = 1;
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}
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/* Save hardware TLB to the vcpu, and invalidate all guest mappings. */
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void kvmppc_44x_tlb_put(struct kvm_vcpu *vcpu)
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{
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struct kvmppc_vcpu_44x *vcpu_44x = to_44x(vcpu);
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int i;
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for (i = 0; i <= tlb_44x_hwater; i++) {
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struct kvmppc_44x_tlbe *stlbe = &vcpu_44x->shadow_tlb[i];
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if (vcpu_44x->shadow_tlb_mod[i])
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kvmppc_44x_tlbre(i, stlbe);
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if (get_tlb_v(stlbe) && get_tlb_ts(stlbe))
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kvmppc_44x_tlbie(i);
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}
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}
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/* Search the guest TLB for a matching entry. */
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int kvmppc_44x_tlb_index(struct kvm_vcpu *vcpu, gva_t eaddr, unsigned int pid,
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unsigned int as)
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{
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struct kvmppc_vcpu_44x *vcpu_44x = to_44x(vcpu);
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int i;
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/* XXX Replace loop with fancy data structures. */
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for (i = 0; i < ARRAY_SIZE(vcpu_44x->guest_tlb); i++) {
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struct kvmppc_44x_tlbe *tlbe = &vcpu_44x->guest_tlb[i];
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unsigned int tid;
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if (eaddr < get_tlb_eaddr(tlbe))
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continue;
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if (eaddr > get_tlb_end(tlbe))
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continue;
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tid = get_tlb_tid(tlbe);
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if (tid && (tid != pid))
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continue;
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if (!get_tlb_v(tlbe))
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continue;
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if (get_tlb_ts(tlbe) != as)
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continue;
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return i;
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}
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return -1;
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}
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gpa_t kvmppc_mmu_xlate(struct kvm_vcpu *vcpu, unsigned int gtlb_index,
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gva_t eaddr)
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{
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struct kvmppc_vcpu_44x *vcpu_44x = to_44x(vcpu);
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struct kvmppc_44x_tlbe *gtlbe = &vcpu_44x->guest_tlb[gtlb_index];
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unsigned int pgmask = get_tlb_bytes(gtlbe) - 1;
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return get_tlb_raddr(gtlbe) | (eaddr & pgmask);
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}
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int kvmppc_mmu_itlb_index(struct kvm_vcpu *vcpu, gva_t eaddr)
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{
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unsigned int as = !!(vcpu->arch.msr & MSR_IS);
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return kvmppc_44x_tlb_index(vcpu, eaddr, vcpu->arch.pid, as);
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}
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int kvmppc_mmu_dtlb_index(struct kvm_vcpu *vcpu, gva_t eaddr)
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{
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unsigned int as = !!(vcpu->arch.msr & MSR_DS);
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return kvmppc_44x_tlb_index(vcpu, eaddr, vcpu->arch.pid, as);
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}
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void kvmppc_mmu_itlb_miss(struct kvm_vcpu *vcpu)
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{
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}
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void kvmppc_mmu_dtlb_miss(struct kvm_vcpu *vcpu)
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{
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}
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static void kvmppc_44x_shadow_release(struct kvmppc_vcpu_44x *vcpu_44x,
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unsigned int stlb_index)
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{
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struct kvmppc_44x_shadow_ref *ref = &vcpu_44x->shadow_refs[stlb_index];
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if (!ref->page)
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return;
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/* Discard from the TLB. */
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/* Note: we could actually invalidate a host mapping, if the host overwrote
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* this TLB entry since we inserted a guest mapping. */
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kvmppc_44x_tlbie(stlb_index);
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/* Now release the page. */
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if (ref->writeable)
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kvm_release_page_dirty(ref->page);
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else
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kvm_release_page_clean(ref->page);
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ref->page = NULL;
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/* XXX set tlb_44x_index to stlb_index? */
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trace_kvm_stlb_inval(stlb_index);
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}
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void kvmppc_mmu_destroy(struct kvm_vcpu *vcpu)
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{
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struct kvmppc_vcpu_44x *vcpu_44x = to_44x(vcpu);
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int i;
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for (i = 0; i <= tlb_44x_hwater; i++)
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kvmppc_44x_shadow_release(vcpu_44x, i);
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}
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/**
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* kvmppc_mmu_map -- create a host mapping for guest memory
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*
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* If the guest wanted a larger page than the host supports, only the first
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* host page is mapped here and the rest are demand faulted.
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*
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* If the guest wanted a smaller page than the host page size, we map only the
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* guest-size page (i.e. not a full host page mapping).
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*
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* Caller must ensure that the specified guest TLB entry is safe to insert into
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* the shadow TLB.
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*/
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void kvmppc_mmu_map(struct kvm_vcpu *vcpu, u64 gvaddr, gpa_t gpaddr,
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unsigned int gtlb_index)
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{
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struct kvmppc_44x_tlbe stlbe;
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struct kvmppc_vcpu_44x *vcpu_44x = to_44x(vcpu);
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struct kvmppc_44x_tlbe *gtlbe = &vcpu_44x->guest_tlb[gtlb_index];
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struct kvmppc_44x_shadow_ref *ref;
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struct page *new_page;
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hpa_t hpaddr;
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gfn_t gfn;
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u32 asid = gtlbe->tid;
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u32 flags = gtlbe->word2;
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u32 max_bytes = get_tlb_bytes(gtlbe);
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unsigned int victim;
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/* Select TLB entry to clobber. Indirectly guard against races with the TLB
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* miss handler by disabling interrupts. */
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local_irq_disable();
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victim = ++tlb_44x_index;
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if (victim > tlb_44x_hwater)
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victim = 0;
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tlb_44x_index = victim;
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local_irq_enable();
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/* Get reference to new page. */
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gfn = gpaddr >> PAGE_SHIFT;
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new_page = gfn_to_page(vcpu->kvm, gfn);
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if (is_error_page(new_page)) {
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printk(KERN_ERR "Couldn't get guest page for gfn %lx!\n", gfn);
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kvm_release_page_clean(new_page);
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return;
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}
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hpaddr = page_to_phys(new_page);
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/* Invalidate any previous shadow mappings. */
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kvmppc_44x_shadow_release(vcpu_44x, victim);
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/* XXX Make sure (va, size) doesn't overlap any other
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* entries. 440x6 user manual says the result would be
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* "undefined." */
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/* XXX what about AS? */
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/* Force TS=1 for all guest mappings. */
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stlbe.word0 = PPC44x_TLB_VALID | PPC44x_TLB_TS;
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if (max_bytes >= PAGE_SIZE) {
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/* Guest mapping is larger than or equal to host page size. We can use
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* a "native" host mapping. */
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stlbe.word0 |= (gvaddr & PAGE_MASK) | PPC44x_TLBE_SIZE;
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} else {
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/* Guest mapping is smaller than host page size. We must restrict the
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* size of the mapping to be at most the smaller of the two, but for
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* simplicity we fall back to a 4K mapping (this is probably what the
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* guest is using anyways). */
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stlbe.word0 |= (gvaddr & PAGE_MASK_4K) | PPC44x_TLB_4K;
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/* 'hpaddr' is a host page, which is larger than the mapping we're
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* inserting here. To compensate, we must add the in-page offset to the
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* sub-page. */
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hpaddr |= gpaddr & (PAGE_MASK ^ PAGE_MASK_4K);
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}
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stlbe.word1 = (hpaddr & 0xfffffc00) | ((hpaddr >> 32) & 0xf);
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stlbe.word2 = kvmppc_44x_tlb_shadow_attrib(flags,
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vcpu->arch.msr & MSR_PR);
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stlbe.tid = !(asid & 0xff);
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/* Keep track of the reference so we can properly release it later. */
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ref = &vcpu_44x->shadow_refs[victim];
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ref->page = new_page;
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ref->gtlb_index = gtlb_index;
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ref->writeable = !!(stlbe.word2 & PPC44x_TLB_UW);
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ref->tid = stlbe.tid;
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/* Insert shadow mapping into hardware TLB. */
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kvmppc_44x_tlbe_set_modified(vcpu_44x, victim);
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kvmppc_44x_tlbwe(victim, &stlbe);
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trace_kvm_stlb_write(victim, stlbe.tid, stlbe.word0, stlbe.word1,
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stlbe.word2);
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}
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/* For a particular guest TLB entry, invalidate the corresponding host TLB
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* mappings and release the host pages. */
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static void kvmppc_44x_invalidate(struct kvm_vcpu *vcpu,
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unsigned int gtlb_index)
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{
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struct kvmppc_vcpu_44x *vcpu_44x = to_44x(vcpu);
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int i;
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for (i = 0; i < ARRAY_SIZE(vcpu_44x->shadow_refs); i++) {
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struct kvmppc_44x_shadow_ref *ref = &vcpu_44x->shadow_refs[i];
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if (ref->gtlb_index == gtlb_index)
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kvmppc_44x_shadow_release(vcpu_44x, i);
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}
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}
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void kvmppc_mmu_priv_switch(struct kvm_vcpu *vcpu, int usermode)
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{
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vcpu->arch.shadow_pid = !usermode;
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}
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void kvmppc_set_pid(struct kvm_vcpu *vcpu, u32 new_pid)
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{
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struct kvmppc_vcpu_44x *vcpu_44x = to_44x(vcpu);
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int i;
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if (unlikely(vcpu->arch.pid == new_pid))
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return;
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vcpu->arch.pid = new_pid;
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/* Guest userspace runs with TID=0 mappings and PID=0, to make sure it
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* can't access guest kernel mappings (TID=1). When we switch to a new
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* guest PID, which will also use host PID=0, we must discard the old guest
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* userspace mappings. */
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for (i = 0; i < ARRAY_SIZE(vcpu_44x->shadow_refs); i++) {
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struct kvmppc_44x_shadow_ref *ref = &vcpu_44x->shadow_refs[i];
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if (ref->tid == 0)
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kvmppc_44x_shadow_release(vcpu_44x, i);
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}
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}
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static int tlbe_is_host_safe(const struct kvm_vcpu *vcpu,
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const struct kvmppc_44x_tlbe *tlbe)
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{
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gpa_t gpa;
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if (!get_tlb_v(tlbe))
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return 0;
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/* Does it match current guest AS? */
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/* XXX what about IS != DS? */
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if (get_tlb_ts(tlbe) != !!(vcpu->arch.msr & MSR_IS))
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return 0;
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gpa = get_tlb_raddr(tlbe);
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if (!gfn_to_memslot(vcpu->kvm, gpa >> PAGE_SHIFT))
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/* Mapping is not for RAM. */
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return 0;
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return 1;
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}
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int kvmppc_44x_emul_tlbwe(struct kvm_vcpu *vcpu, u8 ra, u8 rs, u8 ws)
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{
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struct kvmppc_vcpu_44x *vcpu_44x = to_44x(vcpu);
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struct kvmppc_44x_tlbe *tlbe;
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unsigned int gtlb_index;
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gtlb_index = vcpu->arch.gpr[ra];
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if (gtlb_index > KVM44x_GUEST_TLB_SIZE) {
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printk("%s: index %d\n", __func__, gtlb_index);
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kvmppc_dump_vcpu(vcpu);
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return EMULATE_FAIL;
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}
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tlbe = &vcpu_44x->guest_tlb[gtlb_index];
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/* Invalidate shadow mappings for the about-to-be-clobbered TLB entry. */
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if (tlbe->word0 & PPC44x_TLB_VALID)
|
|
kvmppc_44x_invalidate(vcpu, gtlb_index);
|
|
|
|
switch (ws) {
|
|
case PPC44x_TLB_PAGEID:
|
|
tlbe->tid = get_mmucr_stid(vcpu);
|
|
tlbe->word0 = vcpu->arch.gpr[rs];
|
|
break;
|
|
|
|
case PPC44x_TLB_XLAT:
|
|
tlbe->word1 = vcpu->arch.gpr[rs];
|
|
break;
|
|
|
|
case PPC44x_TLB_ATTRIB:
|
|
tlbe->word2 = vcpu->arch.gpr[rs];
|
|
break;
|
|
|
|
default:
|
|
return EMULATE_FAIL;
|
|
}
|
|
|
|
if (tlbe_is_host_safe(vcpu, tlbe)) {
|
|
gva_t eaddr;
|
|
gpa_t gpaddr;
|
|
u32 bytes;
|
|
|
|
eaddr = get_tlb_eaddr(tlbe);
|
|
gpaddr = get_tlb_raddr(tlbe);
|
|
|
|
/* Use the advertised page size to mask effective and real addrs. */
|
|
bytes = get_tlb_bytes(tlbe);
|
|
eaddr &= ~(bytes - 1);
|
|
gpaddr &= ~(bytes - 1);
|
|
|
|
kvmppc_mmu_map(vcpu, eaddr, gpaddr, gtlb_index);
|
|
}
|
|
|
|
trace_kvm_gtlb_write(gtlb_index, tlbe->tid, tlbe->word0, tlbe->word1,
|
|
tlbe->word2);
|
|
|
|
kvmppc_set_exit_type(vcpu, EMULATED_TLBWE_EXITS);
|
|
return EMULATE_DONE;
|
|
}
|
|
|
|
int kvmppc_44x_emul_tlbsx(struct kvm_vcpu *vcpu, u8 rt, u8 ra, u8 rb, u8 rc)
|
|
{
|
|
u32 ea;
|
|
int gtlb_index;
|
|
unsigned int as = get_mmucr_sts(vcpu);
|
|
unsigned int pid = get_mmucr_stid(vcpu);
|
|
|
|
ea = vcpu->arch.gpr[rb];
|
|
if (ra)
|
|
ea += vcpu->arch.gpr[ra];
|
|
|
|
gtlb_index = kvmppc_44x_tlb_index(vcpu, ea, pid, as);
|
|
if (rc) {
|
|
if (gtlb_index < 0)
|
|
vcpu->arch.cr &= ~0x20000000;
|
|
else
|
|
vcpu->arch.cr |= 0x20000000;
|
|
}
|
|
vcpu->arch.gpr[rt] = gtlb_index;
|
|
|
|
kvmppc_set_exit_type(vcpu, EMULATED_TLBSX_EXITS);
|
|
return EMULATE_DONE;
|
|
}
|