92 lines
3.0 KiB
C
92 lines
3.0 KiB
C
/*
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* A collection of structures, addresses, and values associated with
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* the Freescale MPC86xADS board.
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* Copied from the FADS stuff.
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*
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* Author: MontaVista Software, Inc.
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* source@mvista.com
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*
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* 2005 (c) MontaVista Software, Inc. This file is licensed under the
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* terms of the GNU General Public License version 2. This program is licensed
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* "as is" without any warranty of any kind, whether express or implied.
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*/
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#ifdef __KERNEL__
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#ifndef __ASM_MPC86XADS_H__
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#define __ASM_MPC86XADS_H__
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#include <sysdev/fsl_soc.h>
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/* U-Boot maps BCSR to 0xff080000 */
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#define BCSR_ADDR ((uint)0xff080000)
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#define BCSR_SIZE ((uint)32)
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#define BCSR0 ((uint)(BCSR_ADDR + 0x00))
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#define BCSR1 ((uint)(BCSR_ADDR + 0x04))
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#define BCSR2 ((uint)(BCSR_ADDR + 0x08))
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#define BCSR3 ((uint)(BCSR_ADDR + 0x0c))
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#define BCSR4 ((uint)(BCSR_ADDR + 0x10))
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#define CFG_PHYDEV_ADDR ((uint)0xff0a0000)
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#define BCSR5 ((uint)(CFG_PHYDEV_ADDR + 0x300))
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#define MPC8xx_CPM_OFFSET (0x9c0)
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#define CPM_MAP_ADDR (get_immrbase() + MPC8xx_CPM_OFFSET)
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#define CPM_IRQ_OFFSET 16 // for compability with cpm_uart driver
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#define PCMCIA_MEM_ADDR ((uint)0xff020000)
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#define PCMCIA_MEM_SIZE ((uint)(64 * 1024))
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/* Bits of interest in the BCSRs.
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*/
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#define BCSR1_ETHEN ((uint)0x20000000)
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#define BCSR1_IRDAEN ((uint)0x10000000)
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#define BCSR1_RS232EN_1 ((uint)0x01000000)
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#define BCSR1_PCCEN ((uint)0x00800000)
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#define BCSR1_PCCVCC0 ((uint)0x00400000)
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#define BCSR1_PCCVPP0 ((uint)0x00200000)
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#define BCSR1_PCCVPP1 ((uint)0x00100000)
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#define BCSR1_PCCVPP_MASK (BCSR1_PCCVPP0 | BCSR1_PCCVPP1)
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#define BCSR1_RS232EN_2 ((uint)0x00040000)
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#define BCSR1_PCCVCC1 ((uint)0x00010000)
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#define BCSR1_PCCVCC_MASK (BCSR1_PCCVCC0 | BCSR1_PCCVCC1)
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#define BCSR4_ETH10_RST ((uint)0x80000000) /* 10Base-T PHY reset*/
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#define BCSR4_USB_LO_SPD ((uint)0x04000000)
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#define BCSR4_USB_VCC ((uint)0x02000000)
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#define BCSR4_USB_FULL_SPD ((uint)0x00040000)
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#define BCSR4_USB_EN ((uint)0x00020000)
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#define BCSR5_MII2_EN 0x40
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#define BCSR5_MII2_RST 0x20
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#define BCSR5_T1_RST 0x10
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#define BCSR5_ATM155_RST 0x08
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#define BCSR5_ATM25_RST 0x04
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#define BCSR5_MII1_EN 0x02
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#define BCSR5_MII1_RST 0x01
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/* Interrupt level assignments */
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#define PHY_INTERRUPT SIU_IRQ7 /* PHY link change interrupt */
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#define SIU_INT_FEC1 SIU_LEVEL1 /* FEC1 interrupt */
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#define FEC_INTERRUPT SIU_INT_FEC1 /* FEC interrupt */
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/* We don't use the 8259 */
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#define NR_8259_INTS 0
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/* CPM Ethernet through SCC1 */
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#define PA_ENET_RXD ((ushort)0x0001)
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#define PA_ENET_TXD ((ushort)0x0002)
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#define PA_ENET_TCLK ((ushort)0x0100)
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#define PA_ENET_RCLK ((ushort)0x0200)
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#define PB_ENET_TENA ((uint)0x00001000)
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#define PC_ENET_CLSN ((ushort)0x0010)
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#define PC_ENET_RENA ((ushort)0x0020)
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/* Control bits in the SICR to route TCLK (CLK1) and RCLK (CLK2) to
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* SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
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*/
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#define SICR_ENET_MASK ((uint)0x000000ff)
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#define SICR_ENET_CLKRT ((uint)0x0000002c)
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#endif /* __ASM_MPC86XADS_H__ */
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#endif /* __KERNEL__ */
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