195 lines
6.7 KiB
C
195 lines
6.7 KiB
C
/**************************************************************************
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*
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* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sub license, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
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* IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
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* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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**************************************************************************/
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#ifndef _I915_DRM_H_
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#define _I915_DRM_H_
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/* Please note that modifications to all structs defined here are
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* subject to backwards-compatibility constraints.
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*/
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#include "drm.h"
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/* Each region is a minimum of 16k, and there are at most 255 of them.
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*/
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#define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use
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* of chars for next/prev indices */
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#define I915_LOG_MIN_TEX_REGION_SIZE 14
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typedef struct _drm_i915_init {
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enum {
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I915_INIT_DMA = 0x01,
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I915_CLEANUP_DMA = 0x02,
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I915_RESUME_DMA = 0x03
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} func;
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unsigned int mmio_offset;
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int sarea_priv_offset;
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unsigned int ring_start;
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unsigned int ring_end;
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unsigned int ring_size;
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unsigned int front_offset;
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unsigned int back_offset;
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unsigned int depth_offset;
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unsigned int w;
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unsigned int h;
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unsigned int pitch;
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unsigned int pitch_bits;
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unsigned int back_pitch;
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unsigned int depth_pitch;
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unsigned int cpp;
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unsigned int chipset;
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} drm_i915_init_t;
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typedef struct _drm_i915_sarea {
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drm_tex_region_t texList[I915_NR_TEX_REGIONS + 1];
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int last_upload; /* last time texture was uploaded */
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int last_enqueue; /* last time a buffer was enqueued */
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int last_dispatch; /* age of the most recently dispatched buffer */
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int ctxOwner; /* last context to upload state */
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int texAge;
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int pf_enabled; /* is pageflipping allowed? */
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int pf_active;
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int pf_current_page; /* which buffer is being displayed? */
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int perf_boxes; /* performance boxes to be displayed */
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} drm_i915_sarea_t;
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/* Flags for perf_boxes
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*/
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#define I915_BOX_RING_EMPTY 0x1
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#define I915_BOX_FLIP 0x2
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#define I915_BOX_WAIT 0x4
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#define I915_BOX_TEXTURE_LOAD 0x8
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#define I915_BOX_LOST_CONTEXT 0x10
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/* I915 specific ioctls
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* The device specific ioctl range is 0x40 to 0x79.
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*/
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#define DRM_I915_INIT 0x00
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#define DRM_I915_FLUSH 0x01
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#define DRM_I915_FLIP 0x02
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#define DRM_I915_BATCHBUFFER 0x03
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#define DRM_I915_IRQ_EMIT 0x04
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#define DRM_I915_IRQ_WAIT 0x05
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#define DRM_I915_GETPARAM 0x06
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#define DRM_I915_SETPARAM 0x07
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#define DRM_I915_ALLOC 0x08
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#define DRM_I915_FREE 0x09
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#define DRM_I915_INIT_HEAP 0x0a
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#define DRM_I915_CMDBUFFER 0x0b
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#define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
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#define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
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#define DRM_IOCTL_I915_FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP)
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#define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t)
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#define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t)
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#define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t)
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#define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t)
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#define DRM_IOCTL_I915_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t)
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#define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t)
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#define DRM_IOCTL_I915_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t)
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#define DRM_IOCTL_I915_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t)
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#define DRM_IOCTL_I915_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t)
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/* Allow drivers to submit batchbuffers directly to hardware, relying
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* on the security mechanisms provided by hardware.
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*/
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typedef struct _drm_i915_batchbuffer {
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int start; /* agp offset */
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int used; /* nr bytes in use */
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int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */
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int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */
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int num_cliprects; /* mulitpass with multiple cliprects? */
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drm_clip_rect_t __user *cliprects; /* pointer to userspace cliprects */
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} drm_i915_batchbuffer_t;
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/* As above, but pass a pointer to userspace buffer which can be
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* validated by the kernel prior to sending to hardware.
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*/
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typedef struct _drm_i915_cmdbuffer {
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char __user *buf; /* pointer to userspace command buffer */
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int sz; /* nr bytes in buf */
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int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */
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int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */
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int num_cliprects; /* mulitpass with multiple cliprects? */
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drm_clip_rect_t __user *cliprects; /* pointer to userspace cliprects */
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} drm_i915_cmdbuffer_t;
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/* Userspace can request & wait on irq's:
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*/
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typedef struct drm_i915_irq_emit {
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int __user *irq_seq;
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} drm_i915_irq_emit_t;
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typedef struct drm_i915_irq_wait {
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int irq_seq;
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} drm_i915_irq_wait_t;
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/* Ioctl to query kernel params:
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*/
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#define I915_PARAM_IRQ_ACTIVE 1
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#define I915_PARAM_ALLOW_BATCHBUFFER 2
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typedef struct drm_i915_getparam {
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int param;
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int __user *value;
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} drm_i915_getparam_t;
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/* Ioctl to set kernel params:
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*/
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#define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1
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#define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2
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#define I915_SETPARAM_ALLOW_BATCHBUFFER 3
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typedef struct drm_i915_setparam {
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int param;
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int value;
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} drm_i915_setparam_t;
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/* A memory manager for regions of shared memory:
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*/
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#define I915_MEM_REGION_AGP 1
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typedef struct drm_i915_mem_alloc {
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int region;
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int alignment;
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int size;
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int __user *region_offset; /* offset from start of fb or agp */
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} drm_i915_mem_alloc_t;
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typedef struct drm_i915_mem_free {
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int region;
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int region_offset;
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} drm_i915_mem_free_t;
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typedef struct drm_i915_mem_init_heap {
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int region;
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int size;
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int start;
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} drm_i915_mem_init_heap_t;
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#endif /* _I915_DRM_H_ */
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