40 lines
985 B
C
40 lines
985 B
C
/*
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* arch/sh/kernel/cpu/sh2a/probe.c
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*
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* CPU Subtype Probing for SH-2A.
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*
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* Copyright (C) 2004, 2005 Paul Mundt
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/init.h>
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#include <asm/processor.h>
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#include <asm/cache.h>
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int __init detect_cpu_and_cache_system(void)
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{
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/* Just SH7206 for now .. */
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cpu_data->type = CPU_SH7206;
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cpu_data->dcache.ways = 4;
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cpu_data->dcache.way_incr = (1 << 11);
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cpu_data->dcache.sets = 128;
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cpu_data->dcache.entry_shift = 4;
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cpu_data->dcache.linesz = L1_CACHE_BYTES;
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cpu_data->dcache.flags = 0;
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/*
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* The icache is the same as the dcache as far as this setup is
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* concerned. The only real difference in hardware is that the icache
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* lacks the U bit that the dcache has, none of this has any bearing
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* on the cache info.
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*/
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cpu_data->icache = cpu_data->dcache;
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return 0;
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}
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