516 lines
15 KiB
C
516 lines
15 KiB
C
/*
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* Copyright (C) 2009 ST-Ericsson
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* Copyright (C) 2009 STMicroelectronics
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/list.h>
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#include <linux/errno.h>
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#include <linux/err.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <asm/clkdev.h>
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#include <mach/hardware.h>
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#include "clock.h"
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#define PRCC_PCKEN 0x00
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#define PRCC_PCKDIS 0x04
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#define PRCC_KCKEN 0x08
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#define PRCC_KCKDIS 0x0C
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#define PRCM_YYCLKEN0_MGT_SET 0x510
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#define PRCM_YYCLKEN1_MGT_SET 0x514
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#define PRCM_YYCLKEN0_MGT_CLR 0x518
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#define PRCM_YYCLKEN1_MGT_CLR 0x51C
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#define PRCM_YYCLKEN0_MGT_VAL 0x520
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#define PRCM_YYCLKEN1_MGT_VAL 0x524
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#define PRCM_SVAMMDSPCLK_MGT 0x008
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#define PRCM_SIAMMDSPCLK_MGT 0x00C
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#define PRCM_SGACLK_MGT 0x014
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#define PRCM_UARTCLK_MGT 0x018
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#define PRCM_MSP02CLK_MGT 0x01C
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#define PRCM_MSP1CLK_MGT 0x288
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#define PRCM_I2CCLK_MGT 0x020
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#define PRCM_SDMMCCLK_MGT 0x024
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#define PRCM_SLIMCLK_MGT 0x028
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#define PRCM_PER1CLK_MGT 0x02C
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#define PRCM_PER2CLK_MGT 0x030
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#define PRCM_PER3CLK_MGT 0x034
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#define PRCM_PER5CLK_MGT 0x038
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#define PRCM_PER6CLK_MGT 0x03C
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#define PRCM_PER7CLK_MGT 0x040
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#define PRCM_LCDCLK_MGT 0x044
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#define PRCM_BMLCLK_MGT 0x04C
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#define PRCM_HSITXCLK_MGT 0x050
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#define PRCM_HSIRXCLK_MGT 0x054
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#define PRCM_HDMICLK_MGT 0x058
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#define PRCM_APEATCLK_MGT 0x05C
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#define PRCM_APETRACECLK_MGT 0x060
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#define PRCM_MCDECLK_MGT 0x064
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#define PRCM_IPI2CCLK_MGT 0x068
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#define PRCM_DSIALTCLK_MGT 0x06C
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#define PRCM_DMACLK_MGT 0x074
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#define PRCM_B2R2CLK_MGT 0x078
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#define PRCM_TVCLK_MGT 0x07C
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#define PRCM_UNIPROCLK_MGT 0x278
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#define PRCM_SSPCLK_MGT 0x280
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#define PRCM_RNGCLK_MGT 0x284
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#define PRCM_UICCCLK_MGT 0x27C
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#define PRCM_MGT_ENABLE (1 << 8)
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static DEFINE_SPINLOCK(clocks_lock);
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static void __clk_enable(struct clk *clk)
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{
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if (clk->enabled++ == 0) {
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if (clk->parent_cluster)
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__clk_enable(clk->parent_cluster);
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if (clk->parent_periph)
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__clk_enable(clk->parent_periph);
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if (clk->ops && clk->ops->enable)
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clk->ops->enable(clk);
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}
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}
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int clk_enable(struct clk *clk)
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{
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unsigned long flags;
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spin_lock_irqsave(&clocks_lock, flags);
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__clk_enable(clk);
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spin_unlock_irqrestore(&clocks_lock, flags);
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return 0;
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}
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EXPORT_SYMBOL(clk_enable);
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static void __clk_disable(struct clk *clk)
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{
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if (--clk->enabled == 0) {
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if (clk->ops && clk->ops->disable)
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clk->ops->disable(clk);
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if (clk->parent_periph)
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__clk_disable(clk->parent_periph);
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if (clk->parent_cluster)
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__clk_disable(clk->parent_cluster);
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}
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}
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void clk_disable(struct clk *clk)
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{
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unsigned long flags;
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WARN_ON(!clk->enabled);
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spin_lock_irqsave(&clocks_lock, flags);
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__clk_disable(clk);
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spin_unlock_irqrestore(&clocks_lock, flags);
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}
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EXPORT_SYMBOL(clk_disable);
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unsigned long clk_get_rate(struct clk *clk)
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{
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unsigned long rate;
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if (clk->ops && clk->ops->get_rate)
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return clk->ops->get_rate(clk);
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rate = clk->rate;
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if (!rate) {
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if (clk->parent_periph)
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rate = clk_get_rate(clk->parent_periph);
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else if (clk->parent_cluster)
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rate = clk_get_rate(clk->parent_cluster);
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}
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return rate;
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}
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EXPORT_SYMBOL(clk_get_rate);
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long clk_round_rate(struct clk *clk, unsigned long rate)
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{
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/*TODO*/
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return rate;
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}
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EXPORT_SYMBOL(clk_round_rate);
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int clk_set_rate(struct clk *clk, unsigned long rate)
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{
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clk->rate = rate;
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return 0;
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}
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EXPORT_SYMBOL(clk_set_rate);
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static void clk_prcmu_enable(struct clk *clk)
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{
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void __iomem *cg_set_reg = __io_address(U8500_PRCMU_BASE)
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+ PRCM_YYCLKEN0_MGT_SET + clk->prcmu_cg_off;
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writel(1 << clk->prcmu_cg_bit, cg_set_reg);
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}
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static void clk_prcmu_disable(struct clk *clk)
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{
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void __iomem *cg_clr_reg = __io_address(U8500_PRCMU_BASE)
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+ PRCM_YYCLKEN0_MGT_CLR + clk->prcmu_cg_off;
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writel(1 << clk->prcmu_cg_bit, cg_clr_reg);
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}
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/* ED doesn't have the combined set/clr registers */
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static void clk_prcmu_ed_enable(struct clk *clk)
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{
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void __iomem *addr = __io_address(U8500_PRCMU_BASE)
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+ clk->prcmu_cg_mgt;
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writel(readl(addr) | PRCM_MGT_ENABLE, addr);
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}
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static void clk_prcmu_ed_disable(struct clk *clk)
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{
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void __iomem *addr = __io_address(U8500_PRCMU_BASE)
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+ clk->prcmu_cg_mgt;
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writel(readl(addr) & ~PRCM_MGT_ENABLE, addr);
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}
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static struct clkops clk_prcmu_ops = {
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.enable = clk_prcmu_enable,
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.disable = clk_prcmu_disable,
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};
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static unsigned int clkrst_base[] = {
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[1] = U8500_CLKRST1_BASE,
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[2] = U8500_CLKRST2_BASE,
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[3] = U8500_CLKRST3_BASE,
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[5] = U8500_CLKRST5_BASE,
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[6] = U8500_CLKRST6_BASE,
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[7] = U8500_CLKRST7_BASE_ED,
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};
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static void clk_prcc_enable(struct clk *clk)
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{
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void __iomem *addr = __io_address(clkrst_base[clk->cluster]);
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if (clk->prcc_kernel != -1)
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writel(1 << clk->prcc_kernel, addr + PRCC_KCKEN);
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if (clk->prcc_bus != -1)
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writel(1 << clk->prcc_bus, addr + PRCC_PCKEN);
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}
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static void clk_prcc_disable(struct clk *clk)
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{
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void __iomem *addr = __io_address(clkrst_base[clk->cluster]);
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if (clk->prcc_bus != -1)
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writel(1 << clk->prcc_bus, addr + PRCC_PCKDIS);
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if (clk->prcc_kernel != -1)
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writel(1 << clk->prcc_kernel, addr + PRCC_KCKDIS);
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}
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static struct clkops clk_prcc_ops = {
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.enable = clk_prcc_enable,
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.disable = clk_prcc_disable,
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};
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static struct clk clk_32khz = {
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.rate = 32000,
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};
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/*
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* PRCMU level clock gating
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*/
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/* Bank 0 */
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static DEFINE_PRCMU_CLK(svaclk, 0x0, 2, SVAMMDSPCLK);
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static DEFINE_PRCMU_CLK(siaclk, 0x0, 3, SIAMMDSPCLK);
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static DEFINE_PRCMU_CLK(sgaclk, 0x0, 4, SGACLK);
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static DEFINE_PRCMU_CLK_RATE(uartclk, 0x0, 5, UARTCLK, 38400000);
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static DEFINE_PRCMU_CLK(msp02clk, 0x0, 6, MSP02CLK);
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static DEFINE_PRCMU_CLK(msp1clk, 0x0, 7, MSP1CLK); /* v1 */
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static DEFINE_PRCMU_CLK_RATE(i2cclk, 0x0, 8, I2CCLK, 48000000);
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static DEFINE_PRCMU_CLK_RATE(sdmmcclk, 0x0, 9, SDMMCCLK, 50000000);
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static DEFINE_PRCMU_CLK(slimclk, 0x0, 10, SLIMCLK);
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static DEFINE_PRCMU_CLK(per1clk, 0x0, 11, PER1CLK);
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static DEFINE_PRCMU_CLK(per2clk, 0x0, 12, PER2CLK);
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static DEFINE_PRCMU_CLK(per3clk, 0x0, 13, PER3CLK);
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static DEFINE_PRCMU_CLK(per5clk, 0x0, 14, PER5CLK);
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static DEFINE_PRCMU_CLK_RATE(per6clk, 0x0, 15, PER6CLK, 133330000);
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static DEFINE_PRCMU_CLK_RATE(per7clk, 0x0, 16, PER7CLK, 100000000);
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static DEFINE_PRCMU_CLK(lcdclk, 0x0, 17, LCDCLK);
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static DEFINE_PRCMU_CLK(bmlclk, 0x0, 18, BMLCLK);
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static DEFINE_PRCMU_CLK(hsitxclk, 0x0, 19, HSITXCLK);
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static DEFINE_PRCMU_CLK(hsirxclk, 0x0, 20, HSIRXCLK);
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static DEFINE_PRCMU_CLK(hdmiclk, 0x0, 21, HDMICLK);
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static DEFINE_PRCMU_CLK(apeatclk, 0x0, 22, APEATCLK);
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static DEFINE_PRCMU_CLK(apetraceclk, 0x0, 23, APETRACECLK);
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static DEFINE_PRCMU_CLK(mcdeclk, 0x0, 24, MCDECLK);
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static DEFINE_PRCMU_CLK(ipi2clk, 0x0, 25, IPI2CCLK);
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static DEFINE_PRCMU_CLK(dsialtclk, 0x0, 26, DSIALTCLK); /* v1 */
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static DEFINE_PRCMU_CLK(dmaclk, 0x0, 27, DMACLK);
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static DEFINE_PRCMU_CLK(b2r2clk, 0x0, 28, B2R2CLK);
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static DEFINE_PRCMU_CLK(tvclk, 0x0, 29, TVCLK);
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static DEFINE_PRCMU_CLK(uniproclk, 0x0, 30, UNIPROCLK); /* v1 */
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static DEFINE_PRCMU_CLK_RATE(sspclk, 0x0, 31, SSPCLK, 48000000); /* v1 */
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/* Bank 1 */
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static DEFINE_PRCMU_CLK(rngclk, 0x4, 0, RNGCLK); /* v1 */
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static DEFINE_PRCMU_CLK(uiccclk, 0x4, 1, UICCCLK); /* v1 */
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/*
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* PRCC level clock gating
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* Format: per#, clk, PCKEN bit, KCKEN bit, parent
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*/
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/* Peripheral Cluster #1 */
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static DEFINE_PRCC_CLK(1, i2c4, 10, 9, &clk_i2cclk);
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static DEFINE_PRCC_CLK(1, gpio0, 9, -1, NULL);
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static DEFINE_PRCC_CLK(1, slimbus0, 8, 8, &clk_slimclk);
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static DEFINE_PRCC_CLK(1, spi3_ed, 7, 7, NULL);
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static DEFINE_PRCC_CLK(1, spi3_v1, 7, -1, NULL);
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static DEFINE_PRCC_CLK(1, i2c2, 6, 6, &clk_i2cclk);
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static DEFINE_PRCC_CLK(1, sdi0, 5, 5, &clk_sdmmcclk);
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static DEFINE_PRCC_CLK(1, msp1_ed, 4, 4, &clk_msp02clk);
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static DEFINE_PRCC_CLK(1, msp1_v1, 4, 4, &clk_msp1clk);
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static DEFINE_PRCC_CLK(1, msp0, 3, 3, &clk_msp02clk);
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static DEFINE_PRCC_CLK(1, i2c1, 2, 2, &clk_i2cclk);
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static DEFINE_PRCC_CLK(1, uart1, 1, 1, &clk_uartclk);
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static DEFINE_PRCC_CLK(1, uart0, 0, 0, &clk_uartclk);
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/* Peripheral Cluster #2 */
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static DEFINE_PRCC_CLK(2, gpio1_ed, 12, -1, NULL);
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static DEFINE_PRCC_CLK(2, ssitx_ed, 11, -1, NULL);
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static DEFINE_PRCC_CLK(2, ssirx_ed, 10, -1, NULL);
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static DEFINE_PRCC_CLK(2, spi0_ed, 9, -1, NULL);
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static DEFINE_PRCC_CLK(2, sdi3_ed, 8, 6, &clk_sdmmcclk);
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static DEFINE_PRCC_CLK(2, sdi1_ed, 7, 5, &clk_sdmmcclk);
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static DEFINE_PRCC_CLK(2, msp2_ed, 6, 4, &clk_msp02clk);
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static DEFINE_PRCC_CLK(2, sdi4_ed, 4, 2, &clk_sdmmcclk);
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static DEFINE_PRCC_CLK(2, pwl_ed, 3, 1, NULL);
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static DEFINE_PRCC_CLK(2, spi1_ed, 2, -1, NULL);
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static DEFINE_PRCC_CLK(2, spi2_ed, 1, -1, NULL);
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static DEFINE_PRCC_CLK(2, i2c3_ed, 0, 0, &clk_i2cclk);
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static DEFINE_PRCC_CLK(2, gpio1_v1, 11, -1, NULL);
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static DEFINE_PRCC_CLK(2, ssitx_v1, 10, 7, NULL);
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static DEFINE_PRCC_CLK(2, ssirx_v1, 9, 6, NULL);
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static DEFINE_PRCC_CLK(2, spi0_v1, 8, -1, NULL);
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static DEFINE_PRCC_CLK(2, sdi3_v1, 7, 5, &clk_sdmmcclk);
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static DEFINE_PRCC_CLK(2, sdi1_v1, 6, 4, &clk_sdmmcclk);
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static DEFINE_PRCC_CLK(2, msp2_v1, 5, 3, &clk_msp02clk);
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static DEFINE_PRCC_CLK(2, sdi4_v1, 4, 2, &clk_sdmmcclk);
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static DEFINE_PRCC_CLK(2, pwl_v1, 3, 1, NULL);
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static DEFINE_PRCC_CLK(2, spi1_v1, 2, -1, NULL);
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static DEFINE_PRCC_CLK(2, spi2_v1, 1, -1, NULL);
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static DEFINE_PRCC_CLK(2, i2c3_v1, 0, 0, &clk_i2cclk);
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/* Peripheral Cluster #3 */
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static DEFINE_PRCC_CLK(3, gpio2, 8, -1, NULL);
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static DEFINE_PRCC_CLK(3, sdi5, 7, 7, &clk_sdmmcclk);
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static DEFINE_PRCC_CLK(3, uart2, 6, 6, &clk_uartclk);
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static DEFINE_PRCC_CLK(3, ske, 5, 5, &clk_32khz);
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static DEFINE_PRCC_CLK(3, sdi2, 4, 4, &clk_sdmmcclk);
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static DEFINE_PRCC_CLK(3, i2c0, 3, 3, &clk_i2cclk);
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static DEFINE_PRCC_CLK(3, ssp1_ed, 2, 2, &clk_i2cclk);
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static DEFINE_PRCC_CLK(3, ssp0_ed, 1, 1, &clk_i2cclk);
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static DEFINE_PRCC_CLK(3, ssp1_v1, 2, 2, &clk_sspclk);
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static DEFINE_PRCC_CLK(3, ssp0_v1, 1, 1, &clk_sspclk);
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static DEFINE_PRCC_CLK(3, fsmc, 0, -1, NULL);
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/* Peripheral Cluster #4 is in the always on domain */
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/* Peripheral Cluster #5 */
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static DEFINE_PRCC_CLK(5, gpio3, 1, -1, NULL);
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static DEFINE_PRCC_CLK(5, usb_ed, 0, 0, &clk_i2cclk);
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static DEFINE_PRCC_CLK(5, usb_v1, 0, 0, NULL);
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/* Peripheral Cluster #6 */
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static DEFINE_PRCC_CLK(6, mtu1_v1, 8, -1, NULL);
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static DEFINE_PRCC_CLK(6, mtu0_v1, 7, -1, NULL);
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static DEFINE_PRCC_CLK(6, cfgreg_v1, 6, 6, NULL);
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static DEFINE_PRCC_CLK(6, dmc_ed, 6, 6, NULL);
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static DEFINE_PRCC_CLK(6, hash1, 5, -1, NULL);
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static DEFINE_PRCC_CLK(6, unipro_v1, 4, 1, &clk_uniproclk);
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static DEFINE_PRCC_CLK(6, cryp1_ed, 4, -1, NULL);
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static DEFINE_PRCC_CLK(6, pka, 3, -1, NULL);
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static DEFINE_PRCC_CLK(6, hash0, 2, -1, NULL);
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static DEFINE_PRCC_CLK(6, cryp0, 1, -1, NULL);
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static DEFINE_PRCC_CLK(6, rng_ed, 0, 0, &clk_i2cclk);
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static DEFINE_PRCC_CLK(6, rng_v1, 0, 0, &clk_rngclk);
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/* Peripheral Cluster #7 */
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static DEFINE_PRCC_CLK(7, tzpc0_ed, 4, -1, NULL);
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static DEFINE_PRCC_CLK(7, mtu1_ed, 3, -1, NULL);
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static DEFINE_PRCC_CLK(7, mtu0_ed, 2, -1, NULL);
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static DEFINE_PRCC_CLK(7, wdg_ed, 1, -1, NULL);
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static DEFINE_PRCC_CLK(7, cfgreg_ed, 0, -1, NULL);
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static struct clk_lookup u8500_common_clks[] = {
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/* Peripheral Cluster #1 */
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CLK(gpio0, "gpioblock0", NULL),
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CLK(slimbus0, "slimbus0", NULL),
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CLK(i2c2, "nmk-i2c.2", NULL),
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CLK(sdi0, "sdi0", NULL),
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CLK(msp0, "msp0", NULL),
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CLK(i2c1, "nmk-i2c.1", NULL),
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CLK(uart1, "uart1", NULL),
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CLK(uart0, "uart0", NULL),
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/* Peripheral Cluster #3 */
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CLK(gpio2, "gpioblock2", NULL),
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CLK(sdi5, "sdi5", NULL),
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CLK(uart2, "uart2", NULL),
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CLK(ske, "ske", NULL),
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CLK(sdi2, "sdi2", NULL),
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CLK(i2c0, "nmk-i2c.0", NULL),
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CLK(fsmc, "fsmc", NULL),
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/* Peripheral Cluster #5 */
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CLK(gpio3, "gpioblock3", NULL),
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/* Peripheral Cluster #6 */
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CLK(hash1, "hash1", NULL),
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CLK(pka, "pka", NULL),
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CLK(hash0, "hash0", NULL),
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CLK(cryp0, "cryp0", NULL),
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/* PRCMU level clock gating */
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/* Bank 0 */
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CLK(svaclk, "sva", NULL),
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CLK(siaclk, "sia", NULL),
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CLK(sgaclk, "sga", NULL),
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CLK(slimclk, "slim", NULL),
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|
CLK(lcdclk, "lcd", NULL),
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|
CLK(bmlclk, "bml", NULL),
|
|
CLK(hsitxclk, "stm-hsi.0", NULL),
|
|
CLK(hsirxclk, "stm-hsi.1", NULL),
|
|
CLK(hdmiclk, "hdmi", NULL),
|
|
CLK(apeatclk, "apeat", NULL),
|
|
CLK(apetraceclk, "apetrace", NULL),
|
|
CLK(mcdeclk, "mcde", NULL),
|
|
CLK(ipi2clk, "ipi2", NULL),
|
|
CLK(dmaclk, "dma40", NULL),
|
|
CLK(b2r2clk, "b2r2", NULL),
|
|
CLK(tvclk, "tv", NULL),
|
|
};
|
|
|
|
static struct clk_lookup u8500_ed_clks[] = {
|
|
/* Peripheral Cluster #1 */
|
|
CLK(spi3_ed, "spi3", NULL),
|
|
CLK(msp1_ed, "msp1", NULL),
|
|
|
|
/* Peripheral Cluster #2 */
|
|
CLK(gpio1_ed, "gpioblock1", NULL),
|
|
CLK(ssitx_ed, "ssitx", NULL),
|
|
CLK(ssirx_ed, "ssirx", NULL),
|
|
CLK(spi0_ed, "spi0", NULL),
|
|
CLK(sdi3_ed, "sdi3", NULL),
|
|
CLK(sdi1_ed, "sdi1", NULL),
|
|
CLK(msp2_ed, "msp2", NULL),
|
|
CLK(sdi4_ed, "sdi4", NULL),
|
|
CLK(pwl_ed, "pwl", NULL),
|
|
CLK(spi1_ed, "spi1", NULL),
|
|
CLK(spi2_ed, "spi2", NULL),
|
|
CLK(i2c3_ed, "nmk-i2c.3", NULL),
|
|
|
|
/* Peripheral Cluster #3 */
|
|
CLK(ssp1_ed, "ssp1", NULL),
|
|
CLK(ssp0_ed, "ssp0", NULL),
|
|
|
|
/* Peripheral Cluster #5 */
|
|
CLK(usb_ed, "musb_hdrc.0", "usb"),
|
|
|
|
/* Peripheral Cluster #6 */
|
|
CLK(dmc_ed, "dmc", NULL),
|
|
CLK(cryp1_ed, "cryp1", NULL),
|
|
CLK(rng_ed, "rng", NULL),
|
|
|
|
/* Peripheral Cluster #7 */
|
|
CLK(tzpc0_ed, "tzpc0", NULL),
|
|
CLK(mtu1_ed, "mtu1", NULL),
|
|
CLK(mtu0_ed, "mtu0", NULL),
|
|
CLK(wdg_ed, "wdg", NULL),
|
|
CLK(cfgreg_ed, "cfgreg", NULL),
|
|
};
|
|
|
|
static struct clk_lookup u8500_v1_clks[] = {
|
|
/* Peripheral Cluster #1 */
|
|
CLK(i2c4, "nmk-i2c.4", NULL),
|
|
CLK(spi3_v1, "spi3", NULL),
|
|
CLK(msp1_v1, "msp1", NULL),
|
|
|
|
/* Peripheral Cluster #2 */
|
|
CLK(gpio1_v1, "gpioblock1", NULL),
|
|
CLK(ssitx_v1, "ssitx", NULL),
|
|
CLK(ssirx_v1, "ssirx", NULL),
|
|
CLK(spi0_v1, "spi0", NULL),
|
|
CLK(sdi3_v1, "sdi3", NULL),
|
|
CLK(sdi1_v1, "sdi1", NULL),
|
|
CLK(msp2_v1, "msp2", NULL),
|
|
CLK(sdi4_v1, "sdi4", NULL),
|
|
CLK(pwl_v1, "pwl", NULL),
|
|
CLK(spi1_v1, "spi1", NULL),
|
|
CLK(spi2_v1, "spi2", NULL),
|
|
CLK(i2c3_v1, "nmk-i2c.3", NULL),
|
|
|
|
/* Peripheral Cluster #3 */
|
|
CLK(ssp1_v1, "ssp1", NULL),
|
|
CLK(ssp0_v1, "ssp0", NULL),
|
|
|
|
/* Peripheral Cluster #5 */
|
|
CLK(usb_v1, "musb_hdrc.0", "usb"),
|
|
|
|
/* Peripheral Cluster #6 */
|
|
CLK(mtu1_v1, "mtu1", NULL),
|
|
CLK(mtu0_v1, "mtu0", NULL),
|
|
CLK(cfgreg_v1, "cfgreg", NULL),
|
|
CLK(hash1, "hash1", NULL),
|
|
CLK(unipro_v1, "unipro", NULL),
|
|
CLK(rng_v1, "rng", NULL),
|
|
|
|
/* PRCMU level clock gating */
|
|
|
|
/* Bank 0 */
|
|
CLK(uniproclk, "uniproclk", NULL),
|
|
CLK(dsialtclk, "dsialt", NULL),
|
|
|
|
/* Bank 1 */
|
|
CLK(rngclk, "rng", NULL),
|
|
CLK(uiccclk, "uicc", NULL),
|
|
};
|
|
|
|
static int __init clk_init(void)
|
|
{
|
|
if (cpu_is_u8500ed()) {
|
|
clk_prcmu_ops.enable = clk_prcmu_ed_enable;
|
|
clk_prcmu_ops.disable = clk_prcmu_ed_disable;
|
|
}
|
|
|
|
clkdev_add_table(u8500_common_clks, ARRAY_SIZE(u8500_common_clks));
|
|
if (cpu_is_u8500ed())
|
|
clkdev_add_table(u8500_ed_clks, ARRAY_SIZE(u8500_ed_clks));
|
|
else
|
|
clkdev_add_table(u8500_v1_clks, ARRAY_SIZE(u8500_v1_clks));
|
|
|
|
return 0;
|
|
}
|
|
arch_initcall(clk_init);
|