linux-stable-rt/arch/mips
Thomas Bogendoerfer 14defd90f5 [MIPS] Fix 32bit kernels on R4k with 128 byte cache line size
The generated copy_page for R4k CPU with a 128 byte cache line size used
Create Dirty Exclusive cache line operations even if only part of the
cache line was filled.  This change avoids generating cache operations,
if only part of the cache line size is copied in one loop. It also
increases the maxmimum loop size, because the generated code even fits
into the available space for r4k CPUs with 128 byte cache line size.

Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-07-08 19:33:46 +01:00
..
au1000
basler/excite
bcm47xx
boot
cobalt
configs
dec
emma2rh
fw
gt64120/wrppmc
jazz
jmr3927
kernel
lasat
lemote/lm2e
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math-emu
mips-boards
mipssim
mm
nxp/pnx8550
oprofile
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pmc-sierra
sgi-ip22
sgi-ip27
sgi-ip32
sibyte
sni
tx4927
tx4938
vr41xx
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