611 lines
17 KiB
C
611 lines
17 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* arch/sh64/kernel/time.c
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*
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* Copyright (C) 2000, 2001 Paolo Alberelli
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* Copyright (C) 2003, 2004 Paul Mundt
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* Copyright (C) 2003 Richard Curnow
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*
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* Original TMU/RTC code taken from sh version.
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* Copyright (C) 1999 Tetsuya Okada & Niibe Yutaka
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* Some code taken from i386 version.
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* Copyright (C) 1991, 1992, 1995 Linus Torvalds
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*/
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#include <linux/config.h>
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#include <linux/errno.h>
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#include <linux/rwsem.h>
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#include <linux/sched.h>
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#include <linux/kernel.h>
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#include <linux/param.h>
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#include <linux/string.h>
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#include <linux/mm.h>
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#include <linux/interrupt.h>
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#include <linux/time.h>
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#include <linux/delay.h>
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#include <linux/init.h>
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#include <linux/profile.h>
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#include <linux/smp.h>
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#include <asm/registers.h> /* required by inline __asm__ stmt. */
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#include <asm/processor.h>
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#include <asm/uaccess.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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#include <asm/delay.h>
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#include <linux/timex.h>
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#include <linux/irq.h>
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#include <asm/hardware.h>
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#define TMU_TOCR_INIT 0x00
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#define TMU0_TCR_INIT 0x0020
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#define TMU_TSTR_INIT 1
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#define TMU_TSTR_OFF 0
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/* RCR1 Bits */
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#define RCR1_CF 0x80 /* Carry Flag */
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#define RCR1_CIE 0x10 /* Carry Interrupt Enable */
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#define RCR1_AIE 0x08 /* Alarm Interrupt Enable */
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#define RCR1_AF 0x01 /* Alarm Flag */
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/* RCR2 Bits */
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#define RCR2_PEF 0x80 /* PEriodic interrupt Flag */
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#define RCR2_PESMASK 0x70 /* Periodic interrupt Set */
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#define RCR2_RTCEN 0x08 /* ENable RTC */
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#define RCR2_ADJ 0x04 /* ADJustment (30-second) */
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#define RCR2_RESET 0x02 /* Reset bit */
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#define RCR2_START 0x01 /* Start bit */
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/* Clock, Power and Reset Controller */
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#define CPRC_BLOCK_OFF 0x01010000
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#define CPRC_BASE PHYS_PERIPHERAL_BLOCK + CPRC_BLOCK_OFF
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#define FRQCR (cprc_base+0x0)
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#define WTCSR (cprc_base+0x0018)
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#define STBCR (cprc_base+0x0030)
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/* Time Management Unit */
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#define TMU_BLOCK_OFF 0x01020000
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#define TMU_BASE PHYS_PERIPHERAL_BLOCK + TMU_BLOCK_OFF
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#define TMU0_BASE tmu_base + 0x8 + (0xc * 0x0)
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#define TMU1_BASE tmu_base + 0x8 + (0xc * 0x1)
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#define TMU2_BASE tmu_base + 0x8 + (0xc * 0x2)
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#define TMU_TOCR tmu_base+0x0 /* Byte access */
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#define TMU_TSTR tmu_base+0x4 /* Byte access */
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#define TMU0_TCOR TMU0_BASE+0x0 /* Long access */
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#define TMU0_TCNT TMU0_BASE+0x4 /* Long access */
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#define TMU0_TCR TMU0_BASE+0x8 /* Word access */
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/* Real Time Clock */
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#define RTC_BLOCK_OFF 0x01040000
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#define RTC_BASE PHYS_PERIPHERAL_BLOCK + RTC_BLOCK_OFF
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#define R64CNT rtc_base+0x00
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#define RSECCNT rtc_base+0x04
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#define RMINCNT rtc_base+0x08
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#define RHRCNT rtc_base+0x0c
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#define RWKCNT rtc_base+0x10
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#define RDAYCNT rtc_base+0x14
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#define RMONCNT rtc_base+0x18
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#define RYRCNT rtc_base+0x1c /* 16bit */
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#define RSECAR rtc_base+0x20
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#define RMINAR rtc_base+0x24
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#define RHRAR rtc_base+0x28
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#define RWKAR rtc_base+0x2c
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#define RDAYAR rtc_base+0x30
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#define RMONAR rtc_base+0x34
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#define RCR1 rtc_base+0x38
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#define RCR2 rtc_base+0x3c
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#ifndef BCD_TO_BIN
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#define BCD_TO_BIN(val) ((val)=((val)&15) + ((val)>>4)*10)
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#endif
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#ifndef BIN_TO_BCD
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#define BIN_TO_BCD(val) ((val)=(((val)/10)<<4) + (val)%10)
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#endif
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#define TICK_SIZE (tick_nsec / 1000)
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extern unsigned long wall_jiffies;
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u64 jiffies_64 = INITIAL_JIFFIES;
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static unsigned long tmu_base, rtc_base;
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unsigned long cprc_base;
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/* Variables to allow interpolation of time of day to resolution better than a
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* jiffy. */
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/* This is effectively protected by xtime_lock */
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static unsigned long ctc_last_interrupt;
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static unsigned long long usecs_per_jiffy = 1000000/HZ; /* Approximation */
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#define CTC_JIFFY_SCALE_SHIFT 40
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/* 2**CTC_JIFFY_SCALE_SHIFT / ctc_ticks_per_jiffy */
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static unsigned long long scaled_recip_ctc_ticks_per_jiffy;
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/* Estimate number of microseconds that have elapsed since the last timer tick,
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by scaling the delta that has occured in the CTC register.
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WARNING WARNING WARNING : This algorithm relies on the CTC decrementing at
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the CPU clock rate. If the CPU sleeps, the CTC stops counting. Bear this
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in mind if enabling SLEEP_WORKS in process.c. In that case, this algorithm
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probably needs to use TMU.TCNT0 instead. This will work even if the CPU is
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sleeping, though will be coarser.
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FIXME : What if usecs_per_tick is moving around too much, e.g. if an adjtime
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is running or if the freq or tick arguments of adjtimex are modified after
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we have calibrated the scaling factor? This will result in either a jump at
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the end of a tick period, or a wrap backwards at the start of the next one,
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if the application is reading the time of day often enough. I think we
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ought to do better than this. For this reason, usecs_per_jiffy is left
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separated out in the calculation below. This allows some future hook into
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the adjtime-related stuff in kernel/timer.c to remove this hazard.
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*/
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static unsigned long usecs_since_tick(void)
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{
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unsigned long long current_ctc;
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long ctc_ticks_since_interrupt;
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unsigned long long ull_ctc_ticks_since_interrupt;
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unsigned long result;
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unsigned long long mul1_out;
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unsigned long long mul1_out_high;
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unsigned long long mul2_out_low, mul2_out_high;
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/* Read CTC register */
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asm ("getcon cr62, %0" : "=r" (current_ctc));
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/* Note, the CTC counts down on each CPU clock, not up.
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Note(2), use long type to get correct wraparound arithmetic when
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the counter crosses zero. */
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ctc_ticks_since_interrupt = (long) ctc_last_interrupt - (long) current_ctc;
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ull_ctc_ticks_since_interrupt = (unsigned long long) ctc_ticks_since_interrupt;
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/* Inline assembly to do 32x32x32->64 multiplier */
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asm volatile ("mulu.l %1, %2, %0" :
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"=r" (mul1_out) :
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"r" (ull_ctc_ticks_since_interrupt), "r" (usecs_per_jiffy));
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mul1_out_high = mul1_out >> 32;
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asm volatile ("mulu.l %1, %2, %0" :
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"=r" (mul2_out_low) :
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"r" (mul1_out), "r" (scaled_recip_ctc_ticks_per_jiffy));
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#if 1
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asm volatile ("mulu.l %1, %2, %0" :
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"=r" (mul2_out_high) :
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"r" (mul1_out_high), "r" (scaled_recip_ctc_ticks_per_jiffy));
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#endif
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result = (unsigned long) (((mul2_out_high << 32) + mul2_out_low) >> CTC_JIFFY_SCALE_SHIFT);
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return result;
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}
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void do_gettimeofday(struct timeval *tv)
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{
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unsigned long flags;
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unsigned long seq;
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unsigned long usec, sec;
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do {
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seq = read_seqbegin_irqsave(&xtime_lock, flags);
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usec = usecs_since_tick();
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{
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unsigned long lost = jiffies - wall_jiffies;
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if (lost)
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usec += lost * (1000000 / HZ);
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}
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sec = xtime.tv_sec;
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usec += xtime.tv_nsec / 1000;
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} while (read_seqretry_irqrestore(&xtime_lock, seq, flags));
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while (usec >= 1000000) {
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usec -= 1000000;
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sec++;
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}
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tv->tv_sec = sec;
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tv->tv_usec = usec;
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}
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int do_settimeofday(struct timespec *tv)
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{
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time_t wtm_sec, sec = tv->tv_sec;
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long wtm_nsec, nsec = tv->tv_nsec;
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if ((unsigned long)tv->tv_nsec >= NSEC_PER_SEC)
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return -EINVAL;
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write_seqlock_irq(&xtime_lock);
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/*
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* This is revolting. We need to set "xtime" correctly. However, the
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* value in this location is the value at the most recent update of
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* wall time. Discover what correction gettimeofday() would have
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* made, and then undo it!
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*/
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nsec -= 1000 * (usecs_since_tick() +
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(jiffies - wall_jiffies) * (1000000 / HZ));
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wtm_sec = wall_to_monotonic.tv_sec + (xtime.tv_sec - sec);
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wtm_nsec = wall_to_monotonic.tv_nsec + (xtime.tv_nsec - nsec);
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set_normalized_timespec(&xtime, sec, nsec);
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set_normalized_timespec(&wall_to_monotonic, wtm_sec, wtm_nsec);
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time_adjust = 0; /* stop active adjtime() */
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time_status |= STA_UNSYNC;
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time_maxerror = NTP_PHASE_LIMIT;
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time_esterror = NTP_PHASE_LIMIT;
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write_sequnlock_irq(&xtime_lock);
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clock_was_set();
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return 0;
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}
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static int set_rtc_time(unsigned long nowtime)
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{
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int retval = 0;
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int real_seconds, real_minutes, cmos_minutes;
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ctrl_outb(RCR2_RESET, RCR2); /* Reset pre-scaler & stop RTC */
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cmos_minutes = ctrl_inb(RMINCNT);
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BCD_TO_BIN(cmos_minutes);
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/*
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* since we're only adjusting minutes and seconds,
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* don't interfere with hour overflow. This avoids
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* messing with unknown time zones but requires your
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* RTC not to be off by more than 15 minutes
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*/
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real_seconds = nowtime % 60;
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real_minutes = nowtime / 60;
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if (((abs(real_minutes - cmos_minutes) + 15)/30) & 1)
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real_minutes += 30; /* correct for half hour time zone */
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real_minutes %= 60;
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if (abs(real_minutes - cmos_minutes) < 30) {
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BIN_TO_BCD(real_seconds);
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BIN_TO_BCD(real_minutes);
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ctrl_outb(real_seconds, RSECCNT);
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ctrl_outb(real_minutes, RMINCNT);
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} else {
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printk(KERN_WARNING
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"set_rtc_time: can't update from %d to %d\n",
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cmos_minutes, real_minutes);
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retval = -1;
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}
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ctrl_outb(RCR2_RTCEN|RCR2_START, RCR2); /* Start RTC */
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return retval;
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}
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/* last time the RTC clock got updated */
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static long last_rtc_update = 0;
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/*
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* timer_interrupt() needs to keep up the real-time clock,
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* as well as call the "do_timer()" routine every clocktick
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*/
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static inline void do_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
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{
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unsigned long long current_ctc;
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asm ("getcon cr62, %0" : "=r" (current_ctc));
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ctc_last_interrupt = (unsigned long) current_ctc;
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do_timer(regs);
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#ifndef CONFIG_SMP
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update_process_times(user_mode(regs));
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#endif
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profile_tick(CPU_PROFILING, regs);
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#ifdef CONFIG_HEARTBEAT
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{
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extern void heartbeat(void);
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heartbeat();
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}
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#endif
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/*
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* If we have an externally synchronized Linux clock, then update
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* RTC clock accordingly every ~11 minutes. Set_rtc_mmss() has to be
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* called as close as possible to 500 ms before the new second starts.
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*/
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if ((time_status & STA_UNSYNC) == 0 &&
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xtime.tv_sec > last_rtc_update + 660 &&
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(xtime.tv_nsec / 1000) >= 500000 - ((unsigned) TICK_SIZE) / 2 &&
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(xtime.tv_nsec / 1000) <= 500000 + ((unsigned) TICK_SIZE) / 2) {
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if (set_rtc_time(xtime.tv_sec) == 0)
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last_rtc_update = xtime.tv_sec;
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else
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last_rtc_update = xtime.tv_sec - 600; /* do it again in 60 s */
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}
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}
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/*
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* This is the same as the above, except we _also_ save the current
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* Time Stamp Counter value at the time of the timer interrupt, so that
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* we later on can estimate the time of day more exactly.
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*/
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static irqreturn_t timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
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{
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unsigned long timer_status;
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/* Clear UNF bit */
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timer_status = ctrl_inw(TMU0_TCR);
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timer_status &= ~0x100;
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ctrl_outw(timer_status, TMU0_TCR);
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/*
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* Here we are in the timer irq handler. We just have irqs locally
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* disabled but we don't know if the timer_bh is running on the other
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* CPU. We need to avoid to SMP race with it. NOTE: we don' t need
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* the irq version of write_lock because as just said we have irq
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* locally disabled. -arca
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*/
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write_lock(&xtime_lock);
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do_timer_interrupt(irq, NULL, regs);
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write_unlock(&xtime_lock);
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return IRQ_HANDLED;
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}
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static unsigned long get_rtc_time(void)
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{
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unsigned int sec, min, hr, wk, day, mon, yr, yr100;
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again:
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do {
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ctrl_outb(0, RCR1); /* Clear CF-bit */
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sec = ctrl_inb(RSECCNT);
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min = ctrl_inb(RMINCNT);
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hr = ctrl_inb(RHRCNT);
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wk = ctrl_inb(RWKCNT);
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day = ctrl_inb(RDAYCNT);
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mon = ctrl_inb(RMONCNT);
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yr = ctrl_inw(RYRCNT);
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yr100 = (yr >> 8);
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yr &= 0xff;
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} while ((ctrl_inb(RCR1) & RCR1_CF) != 0);
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BCD_TO_BIN(yr100);
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BCD_TO_BIN(yr);
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BCD_TO_BIN(mon);
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BCD_TO_BIN(day);
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BCD_TO_BIN(hr);
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BCD_TO_BIN(min);
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BCD_TO_BIN(sec);
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if (yr > 99 || mon < 1 || mon > 12 || day > 31 || day < 1 ||
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hr > 23 || min > 59 || sec > 59) {
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printk(KERN_ERR
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"SH RTC: invalid value, resetting to 1 Jan 2000\n");
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ctrl_outb(RCR2_RESET, RCR2); /* Reset & Stop */
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ctrl_outb(0, RSECCNT);
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ctrl_outb(0, RMINCNT);
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ctrl_outb(0, RHRCNT);
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ctrl_outb(6, RWKCNT);
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ctrl_outb(1, RDAYCNT);
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ctrl_outb(1, RMONCNT);
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ctrl_outw(0x2000, RYRCNT);
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ctrl_outb(RCR2_RTCEN|RCR2_START, RCR2); /* Start */
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goto again;
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}
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return mktime(yr100 * 100 + yr, mon, day, hr, min, sec);
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}
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static __init unsigned int get_cpu_hz(void)
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{
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unsigned int count;
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unsigned long __dummy;
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unsigned long ctc_val_init, ctc_val;
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/*
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** Regardless the toolchain, force the compiler to use the
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** arbitrary register r3 as a clock tick counter.
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** NOTE: r3 must be in accordance with rtc_interrupt()
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*/
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register unsigned long long __rtc_irq_flag __asm__ ("r3");
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local_irq_enable();
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do {} while (ctrl_inb(R64CNT) != 0);
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ctrl_outb(RCR1_CIE, RCR1); /* Enable carry interrupt */
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/*
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* r3 is arbitrary. CDC does not support "=z".
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*/
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ctc_val_init = 0xffffffff;
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ctc_val = ctc_val_init;
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asm volatile("gettr tr0, %1\n\t"
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"putcon %0, " __CTC "\n\t"
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"and %2, r63, %2\n\t"
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"pta $+4, tr0\n\t"
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"beq/l %2, r63, tr0\n\t"
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"ptabs %1, tr0\n\t"
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"getcon " __CTC ", %0\n\t"
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: "=r"(ctc_val), "=r" (__dummy), "=r" (__rtc_irq_flag)
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: "0" (0));
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local_irq_disable();
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/*
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* SH-3:
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* CPU clock = 4 stages * loop
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* tst rm,rm if id ex
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* bt/s 1b if id ex
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* add #1,rd if id ex
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* (if) pipe line stole
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* tst rm,rm if id ex
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* ....
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*
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*
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* SH-4:
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* CPU clock = 6 stages * loop
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* I don't know why.
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* ....
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*
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* SH-5:
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* Use CTC register to count. This approach returns the right value
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* even if the I-cache is disabled (e.g. whilst debugging.)
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*
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*/
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count = ctc_val_init - ctc_val; /* CTC counts down */
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#if defined (CONFIG_SH_SIMULATOR)
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/*
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* Let's pretend we are a 5MHz SH-5 to avoid a too
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* little timer interval. Also to keep delay
|
|
* calibration within a reasonable time.
|
|
*/
|
|
return 5000000;
|
|
#else
|
|
/*
|
|
* This really is count by the number of clock cycles
|
|
* by the ratio between a complete R64CNT
|
|
* wrap-around (128) and CUI interrupt being raised (64).
|
|
*/
|
|
return count*2;
|
|
#endif
|
|
}
|
|
|
|
static irqreturn_t rtc_interrupt(int irq, void *dev_id, struct pt_regs *regs)
|
|
{
|
|
ctrl_outb(0, RCR1); /* Disable Carry Interrupts */
|
|
regs->regs[3] = 1; /* Using r3 */
|
|
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
static struct irqaction irq0 = { timer_interrupt, SA_INTERRUPT, CPU_MASK_NONE, "timer", NULL, NULL};
|
|
static struct irqaction irq1 = { rtc_interrupt, SA_INTERRUPT, CPU_MASK_NONE, "rtc", NULL, NULL};
|
|
|
|
void __init time_init(void)
|
|
{
|
|
unsigned int cpu_clock, master_clock, bus_clock, module_clock;
|
|
unsigned long interval;
|
|
unsigned long frqcr, ifc, pfc;
|
|
static int ifc_table[] = { 2, 4, 6, 8, 10, 12, 16, 24 };
|
|
#define bfc_table ifc_table /* Same */
|
|
#define pfc_table ifc_table /* Same */
|
|
|
|
tmu_base = onchip_remap(TMU_BASE, 1024, "TMU");
|
|
if (!tmu_base) {
|
|
panic("Unable to remap TMU\n");
|
|
}
|
|
|
|
rtc_base = onchip_remap(RTC_BASE, 1024, "RTC");
|
|
if (!rtc_base) {
|
|
panic("Unable to remap RTC\n");
|
|
}
|
|
|
|
cprc_base = onchip_remap(CPRC_BASE, 1024, "CPRC");
|
|
if (!cprc_base) {
|
|
panic("Unable to remap CPRC\n");
|
|
}
|
|
|
|
xtime.tv_sec = get_rtc_time();
|
|
xtime.tv_nsec = 0;
|
|
|
|
setup_irq(TIMER_IRQ, &irq0);
|
|
setup_irq(RTC_IRQ, &irq1);
|
|
|
|
/* Check how fast it is.. */
|
|
cpu_clock = get_cpu_hz();
|
|
|
|
/* Note careful order of operations to maintain reasonable precision and avoid overflow. */
|
|
scaled_recip_ctc_ticks_per_jiffy = ((1ULL << CTC_JIFFY_SCALE_SHIFT) / (unsigned long long)(cpu_clock / HZ));
|
|
|
|
disable_irq(RTC_IRQ);
|
|
|
|
printk("CPU clock: %d.%02dMHz\n",
|
|
(cpu_clock / 1000000), (cpu_clock % 1000000)/10000);
|
|
{
|
|
unsigned short bfc;
|
|
frqcr = ctrl_inl(FRQCR);
|
|
ifc = ifc_table[(frqcr>> 6) & 0x0007];
|
|
bfc = bfc_table[(frqcr>> 3) & 0x0007];
|
|
pfc = pfc_table[(frqcr>> 12) & 0x0007];
|
|
master_clock = cpu_clock * ifc;
|
|
bus_clock = master_clock/bfc;
|
|
}
|
|
|
|
printk("Bus clock: %d.%02dMHz\n",
|
|
(bus_clock/1000000), (bus_clock % 1000000)/10000);
|
|
module_clock = master_clock/pfc;
|
|
printk("Module clock: %d.%02dMHz\n",
|
|
(module_clock/1000000), (module_clock % 1000000)/10000);
|
|
interval = (module_clock/(HZ*4));
|
|
|
|
printk("Interval = %ld\n", interval);
|
|
|
|
current_cpu_data.cpu_clock = cpu_clock;
|
|
current_cpu_data.master_clock = master_clock;
|
|
current_cpu_data.bus_clock = bus_clock;
|
|
current_cpu_data.module_clock = module_clock;
|
|
|
|
/* Start TMU0 */
|
|
ctrl_outb(TMU_TSTR_OFF, TMU_TSTR);
|
|
ctrl_outb(TMU_TOCR_INIT, TMU_TOCR);
|
|
ctrl_outw(TMU0_TCR_INIT, TMU0_TCR);
|
|
ctrl_outl(interval, TMU0_TCOR);
|
|
ctrl_outl(interval, TMU0_TCNT);
|
|
ctrl_outb(TMU_TSTR_INIT, TMU_TSTR);
|
|
}
|
|
|
|
void enter_deep_standby(void)
|
|
{
|
|
/* Disable watchdog timer */
|
|
ctrl_outl(0xa5000000, WTCSR);
|
|
/* Configure deep standby on sleep */
|
|
ctrl_outl(0x03, STBCR);
|
|
|
|
#ifdef CONFIG_SH_ALPHANUMERIC
|
|
{
|
|
extern void mach_alphanum(int position, unsigned char value);
|
|
extern void mach_alphanum_brightness(int setting);
|
|
char halted[] = "Halted. ";
|
|
int i;
|
|
mach_alphanum_brightness(6); /* dimmest setting above off */
|
|
for (i=0; i<8; i++) {
|
|
mach_alphanum(i, halted[i]);
|
|
}
|
|
asm __volatile__ ("synco");
|
|
}
|
|
#endif
|
|
|
|
asm __volatile__ ("sleep");
|
|
asm __volatile__ ("synci");
|
|
asm __volatile__ ("nop");
|
|
asm __volatile__ ("nop");
|
|
asm __volatile__ ("nop");
|
|
asm __volatile__ ("nop");
|
|
panic("Unexpected wakeup!\n");
|
|
}
|
|
|
|
/*
|
|
* Scheduler clock - returns current time in nanosec units.
|
|
*/
|
|
unsigned long long sched_clock(void)
|
|
{
|
|
return (unsigned long long)jiffies * (1000000000 / HZ);
|
|
}
|
|
|