156 lines
3.9 KiB
C
156 lines
3.9 KiB
C
/* arch/sh/kernel/pci.c
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* $Id: pci.c,v 1.1 2003/08/24 19:15:45 lethal Exp $
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*
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* Copyright (c) 2002 M. R. Brown <mrbrown@linux-sh.org>
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*
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*
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* These functions are collected here to reduce duplication of common
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* code amongst the many platform-specific PCI support code files.
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*
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* These routines require the following board-specific routines:
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* void pcibios_fixup_irqs();
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*
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* See include/asm-sh/pci.h for more information.
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*/
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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static int __init pcibios_init(void)
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{
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struct pci_channel *p;
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struct pci_bus *bus;
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int busno;
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#ifdef CONFIG_PCI_AUTO
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/* assign resources */
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busno = 0;
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for (p = board_pci_channels; p->pci_ops != NULL; p++) {
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busno = pciauto_assign_resources(busno, p) + 1;
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}
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#endif
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/* scan the buses */
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busno = 0;
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for (p= board_pci_channels; p->pci_ops != NULL; p++) {
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bus = pci_scan_bus(busno, p->pci_ops, p);
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busno = bus->subordinate+1;
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}
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/* board-specific fixups */
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pcibios_fixup_irqs();
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return 0;
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}
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subsys_initcall(pcibios_init);
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void
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pcibios_update_resource(struct pci_dev *dev, struct resource *root,
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struct resource *res, int resource)
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{
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u32 new, check;
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int reg;
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new = res->start | (res->flags & PCI_REGION_FLAG_MASK);
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if (resource < 6) {
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reg = PCI_BASE_ADDRESS_0 + 4*resource;
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} else if (resource == PCI_ROM_RESOURCE) {
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res->flags |= IORESOURCE_ROM_ENABLE;
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new |= PCI_ROM_ADDRESS_ENABLE;
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reg = dev->rom_base_reg;
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} else {
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/* Somebody might have asked allocation of a non-standard resource */
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return;
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}
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pci_write_config_dword(dev, reg, new);
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pci_read_config_dword(dev, reg, &check);
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if ((new ^ check) & ((new & PCI_BASE_ADDRESS_SPACE_IO) ? PCI_BASE_ADDRESS_IO_MASK : PCI_BASE_ADDRESS_MEM_MASK)) {
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printk(KERN_ERR "PCI: Error while updating region "
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"%s/%d (%08x != %08x)\n", pci_name(dev), resource,
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new, check);
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}
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}
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void pcibios_align_resource(void *data, struct resource *res,
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unsigned long size, unsigned long align)
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__attribute__ ((weak));
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/*
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* We need to avoid collisions with `mirrored' VGA ports
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* and other strange ISA hardware, so we always want the
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* addresses to be allocated in the 0x000-0x0ff region
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* modulo 0x400.
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*/
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void pcibios_align_resource(void *data, struct resource *res,
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unsigned long size, unsigned long align)
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{
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if (res->flags & IORESOURCE_IO) {
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unsigned long start = res->start;
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if (start & 0x300) {
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start = (start + 0x3ff) & ~0x3ff;
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res->start = start;
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}
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}
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}
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int pcibios_enable_device(struct pci_dev *dev, int mask)
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{
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u16 cmd, old_cmd;
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int idx;
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struct resource *r;
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pci_read_config_word(dev, PCI_COMMAND, &cmd);
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old_cmd = cmd;
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for(idx=0; idx<6; idx++) {
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if (!(mask & (1 << idx)))
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continue;
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r = &dev->resource[idx];
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if (!r->start && r->end) {
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printk(KERN_ERR "PCI: Device %s not available because "
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"of resource collisions\n", pci_name(dev));
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return -EINVAL;
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}
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if (r->flags & IORESOURCE_IO)
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cmd |= PCI_COMMAND_IO;
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if (r->flags & IORESOURCE_MEM)
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cmd |= PCI_COMMAND_MEMORY;
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}
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if (dev->resource[PCI_ROM_RESOURCE].start)
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cmd |= PCI_COMMAND_MEMORY;
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if (cmd != old_cmd) {
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printk(KERN_INFO "PCI: Enabling device %s (%04x -> %04x)\n",
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pci_name(dev), old_cmd, cmd);
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pci_write_config_word(dev, PCI_COMMAND, cmd);
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}
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return 0;
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}
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/*
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* If we set up a device for bus mastering, we need to check and set
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* the latency timer as it may not be properly set.
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*/
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unsigned int pcibios_max_latency = 255;
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void pcibios_set_master(struct pci_dev *dev)
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{
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u8 lat;
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pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
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if (lat < 16)
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lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
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else if (lat > pcibios_max_latency)
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lat = pcibios_max_latency;
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else
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return;
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printk(KERN_INFO "PCI: Setting latency timer of device %s to %d\n", pci_name(dev), lat);
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pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
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}
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void __init pcibios_update_irq(struct pci_dev *dev, int irq)
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{
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pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
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}
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