271 lines
6.7 KiB
C
271 lines
6.7 KiB
C
/* Definitions for Xtensa instructions, types, and protos. */
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/*
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* Copyright (c) 2003 Tensilica, Inc. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of version 2.1 of the GNU Lesser General Public
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* License as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it would be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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*
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* Further, this software is distributed without any warranty that it is
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* free of the rightful claim of any third person regarding infringement
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* or the like. Any license provided herein, whether implied or
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* otherwise, applies only to this software file. Patent licenses, if
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* any, provided herein do not apply to combinations of this program with
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* other software, or any other product whatsoever.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this program; if not, write the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307,
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* USA.
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*/
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/* Do not modify. This is automatically generated.*/
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#ifndef _XTENSA_BASE_HEADER
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#define _XTENSA_BASE_HEADER
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#ifdef __XTENSA__
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#if defined(__GNUC__) && !defined(__XCC__)
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#define L8UI_ASM(arr, ars, imm) { \
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__asm__ volatile("l8ui %0, %1, %2" : "=a" (arr) : "a" (ars) , "i" (imm)); \
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}
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#define XT_L8UI(ars, imm) \
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({ \
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unsigned char _arr; \
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const unsigned char *_ars = ars; \
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L8UI_ASM(_arr, _ars, imm); \
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_arr; \
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})
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#define L16UI_ASM(arr, ars, imm) { \
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__asm__ volatile("l16ui %0, %1, %2" : "=a" (arr) : "a" (ars) , "i" (imm)); \
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}
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#define XT_L16UI(ars, imm) \
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({ \
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unsigned short _arr; \
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const unsigned short *_ars = ars; \
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L16UI_ASM(_arr, _ars, imm); \
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_arr; \
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})
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#define L16SI_ASM(arr, ars, imm) {\
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__asm__ volatile("l16si %0, %1, %2" : "=a" (arr) : "a" (ars) , "i" (imm)); \
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}
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#define XT_L16SI(ars, imm) \
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({ \
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signed short _arr; \
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const signed short *_ars = ars; \
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L16SI_ASM(_arr, _ars, imm); \
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_arr; \
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})
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#define L32I_ASM(arr, ars, imm) { \
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__asm__ volatile("l32i %0, %1, %2" : "=a" (arr) : "a" (ars) , "i" (imm)); \
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}
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#define XT_L32I(ars, imm) \
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({ \
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unsigned _arr; \
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const unsigned *_ars = ars; \
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L32I_ASM(_arr, _ars, imm); \
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_arr; \
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})
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#define S8I_ASM(arr, ars, imm) {\
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__asm__ volatile("s8i %0, %1, %2" : : "a" (arr), "a" (ars) , "i" (imm) : "memory" ); \
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}
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#define XT_S8I(arr, ars, imm) \
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({ \
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signed char _arr = arr; \
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const signed char *_ars = ars; \
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S8I_ASM(_arr, _ars, imm); \
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})
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#define S16I_ASM(arr, ars, imm) {\
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__asm__ volatile("s16i %0, %1, %2" : : "a" (arr), "a" (ars) , "i" (imm) : "memory" ); \
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}
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#define XT_S16I(arr, ars, imm) \
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({ \
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signed short _arr = arr; \
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const signed short *_ars = ars; \
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S16I_ASM(_arr, _ars, imm); \
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})
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#define S32I_ASM(arr, ars, imm) { \
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__asm__ volatile("s32i %0, %1, %2" : : "a" (arr), "a" (ars) , "i" (imm) : "memory" ); \
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}
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#define XT_S32I(arr, ars, imm) \
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({ \
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signed int _arr = arr; \
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const signed int *_ars = ars; \
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S32I_ASM(_arr, _ars, imm); \
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})
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#define ADDI_ASM(art, ars, imm) {\
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__asm__ ("addi %0, %1, %2" : "=a" (art) : "a" (ars), "i" (imm)); \
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}
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#define XT_ADDI(ars, imm) \
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({ \
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unsigned _art; \
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unsigned _ars = ars; \
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ADDI_ASM(_art, _ars, imm); \
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_art; \
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})
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#define ABS_ASM(arr, art) {\
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__asm__ ("abs %0, %1" : "=a" (arr) : "a" (art)); \
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}
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#define XT_ABS(art) \
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({ \
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unsigned _arr; \
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signed _art = art; \
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ABS_ASM(_arr, _art); \
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_arr; \
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})
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/* Note: In the following macros that reference SAR, the magic "state"
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register is used to capture the dependency on SAR. This is because
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SAR is a 5-bit register and thus there are no C types that can be
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used to represent it. It doesn't appear that the SAR register is
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even relevant to GCC, but it is marked as "clobbered" just in
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case. */
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#define SRC_ASM(arr, ars, art) {\
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register int _xt_sar __asm__ ("state"); \
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__asm__ ("src %0, %1, %2" \
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: "=a" (arr) : "a" (ars), "a" (art), "t" (_xt_sar)); \
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}
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#define XT_SRC(ars, art) \
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({ \
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unsigned _arr; \
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unsigned _ars = ars; \
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unsigned _art = art; \
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SRC_ASM(_arr, _ars, _art); \
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_arr; \
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})
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#define SSR_ASM(ars) {\
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register int _xt_sar __asm__ ("state"); \
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__asm__ ("ssr %1" : "=t" (_xt_sar) : "a" (ars) : "sar"); \
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}
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#define XT_SSR(ars) \
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({ \
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unsigned _ars = ars; \
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SSR_ASM(_ars); \
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})
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#define SSL_ASM(ars) {\
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register int _xt_sar __asm__ ("state"); \
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__asm__ ("ssl %1" : "=t" (_xt_sar) : "a" (ars) : "sar"); \
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}
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#define XT_SSL(ars) \
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({ \
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unsigned _ars = ars; \
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SSL_ASM(_ars); \
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})
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#define SSA8B_ASM(ars) {\
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register int _xt_sar __asm__ ("state"); \
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__asm__ ("ssa8b %1" : "=t" (_xt_sar) : "a" (ars) : "sar"); \
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}
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#define XT_SSA8B(ars) \
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({ \
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unsigned _ars = ars; \
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SSA8B_ASM(_ars); \
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})
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#define SSA8L_ASM(ars) {\
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register int _xt_sar __asm__ ("state"); \
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__asm__ ("ssa8l %1" : "=t" (_xt_sar) : "a" (ars) : "sar"); \
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}
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#define XT_SSA8L(ars) \
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({ \
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unsigned _ars = ars; \
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SSA8L_ASM(_ars); \
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})
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#define SSAI_ASM(imm) {\
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register int _xt_sar __asm__ ("state"); \
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__asm__ ("ssai %1" : "=t" (_xt_sar) : "i" (imm) : "sar"); \
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}
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#define XT_SSAI(imm) \
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({ \
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SSAI_ASM(imm); \
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})
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#endif /* __GNUC__ && !__XCC__ */
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#ifdef __XCC__
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/* Core load/store instructions */
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extern unsigned char _TIE_L8UI(const unsigned char * ars, immediate imm);
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extern unsigned short _TIE_L16UI(const unsigned short * ars, immediate imm);
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extern signed short _TIE_L16SI(const signed short * ars, immediate imm);
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extern unsigned _TIE_L32I(const unsigned * ars, immediate imm);
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extern void _TIE_S8I(unsigned char arr, unsigned char * ars, immediate imm);
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extern void _TIE_S16I(unsigned short arr, unsigned short * ars, immediate imm);
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extern void _TIE_S32I(unsigned arr, unsigned * ars, immediate imm);
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#define XT_L8UI _TIE_L8UI
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#define XT_L16UI _TIE_L16UI
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#define XT_L16SI _TIE_L16SI
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#define XT_L32I _TIE_L32I
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#define XT_S8I _TIE_S8I
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#define XT_S16I _TIE_S16I
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#define XT_S32I _TIE_S32I
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/* Add-immediate instruction */
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extern unsigned _TIE_ADDI(unsigned ars, immediate imm);
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#define XT_ADDI _TIE_ADDI
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/* Absolute value instruction */
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extern unsigned _TIE_ABS(int art);
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#define XT_ABS _TIE_ABS
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/* funnel shift instructions */
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extern unsigned _TIE_SRC(unsigned ars, unsigned art);
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#define XT_SRC _TIE_SRC
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extern void _TIE_SSR(unsigned ars);
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#define XT_SSR _TIE_SSR
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extern void _TIE_SSL(unsigned ars);
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#define XT_SSL _TIE_SSL
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extern void _TIE_SSA8B(unsigned ars);
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#define XT_SSA8B _TIE_SSA8B
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extern void _TIE_SSA8L(unsigned ars);
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#define XT_SSA8L _TIE_SSA8L
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extern void _TIE_SSAI(immediate imm);
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#define XT_SSAI _TIE_SSAI
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#endif /* __XCC__ */
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#endif /* __XTENSA__ */
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#endif /* !_XTENSA_BASE_HEADER */
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