157 lines
4.7 KiB
C
157 lines
4.7 KiB
C
/*
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* A collection of structures, addresses, and values associated with
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* the Motorola 860T FADS board. Copied from the MBX stuff.
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*
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* Copyright (c) 1998 Dan Malek (dmalek@jlc.net)
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*
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* Added MPC86XADS support.
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* The MPC86xADS manual says the board "is compatible with the MPC8xxFADS
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* for SW point of view". This is 99% correct.
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*
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* Author: MontaVista Software, Inc.
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* source@mvista.com
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* 2005 (c) MontaVista Software, Inc. This file is licensed under the
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* terms of the GNU General Public License version 2. This program is licensed
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* "as is" without any warranty of any kind, whether express or implied.
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*/
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#ifdef __KERNEL__
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#ifndef __ASM_FADS_H__
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#define __ASM_FADS_H__
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#include <linux/config.h>
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#include <asm/ppcboot.h>
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#if defined(CONFIG_MPC86XADS)
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#define BOARD_CHIP_NAME "MPC86X"
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/* U-Boot maps BCSR to 0xff080000 */
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#define BCSR_ADDR ((uint)0xff080000)
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/* MPC86XADS has one more CPLD and an additional BCSR.
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*/
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#define CFG_PHYDEV_ADDR ((uint)0xff0a0000)
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#define BCSR5 ((uint)(CFG_PHYDEV_ADDR + 0x300))
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#define BCSR5_T1_RST 0x10
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#define BCSR5_ATM155_RST 0x08
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#define BCSR5_ATM25_RST 0x04
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#define BCSR5_MII1_EN 0x02
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#define BCSR5_MII1_RST 0x01
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/* There is no PHY link change interrupt */
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#define PHY_INTERRUPT (-1)
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#else /* FADS */
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/* Memory map is configured by the PROM startup.
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* I tried to follow the FADS manual, although the startup PROM
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* dictates this and we simply have to move some of the physical
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* addresses for Linux.
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*/
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#define BCSR_ADDR ((uint)0xff010000)
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/* PHY link change interrupt */
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#define PHY_INTERRUPT SIU_IRQ2
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#endif /* CONFIG_MPC86XADS */
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#define BCSR_SIZE ((uint)(64 * 1024))
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#define BCSR0 ((uint)(BCSR_ADDR + 0x00))
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#define BCSR1 ((uint)(BCSR_ADDR + 0x04))
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#define BCSR2 ((uint)(BCSR_ADDR + 0x08))
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#define BCSR3 ((uint)(BCSR_ADDR + 0x0c))
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#define BCSR4 ((uint)(BCSR_ADDR + 0x10))
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#define IMAP_ADDR ((uint)0xff000000)
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#define IMAP_SIZE ((uint)(64 * 1024))
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#define PCMCIA_MEM_ADDR ((uint)0xff020000)
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#define PCMCIA_MEM_SIZE ((uint)(64 * 1024))
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/* Bits of interest in the BCSRs.
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*/
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#define BCSR1_ETHEN ((uint)0x20000000)
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#define BCSR1_IRDAEN ((uint)0x10000000)
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#define BCSR1_RS232EN_1 ((uint)0x01000000)
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#define BCSR1_PCCEN ((uint)0x00800000)
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#define BCSR1_PCCVCC0 ((uint)0x00400000)
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#define BCSR1_PCCVPP0 ((uint)0x00200000)
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#define BCSR1_PCCVPP1 ((uint)0x00100000)
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#define BCSR1_PCCVPP_MASK (BCSR1_PCCVPP0 | BCSR1_PCCVPP1)
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#define BCSR1_RS232EN_2 ((uint)0x00040000)
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#define BCSR1_PCCVCC1 ((uint)0x00010000)
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#define BCSR1_PCCVCC_MASK (BCSR1_PCCVCC0 | BCSR1_PCCVCC1)
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#define BCSR4_ETHLOOP ((uint)0x80000000) /* EEST Loopback */
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#define BCSR4_EEFDX ((uint)0x40000000) /* EEST FDX enable */
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#define BCSR4_FETH_EN ((uint)0x08000000) /* PHY enable */
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#define BCSR4_FETHCFG0 ((uint)0x04000000) /* PHY autoneg mode */
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#define BCSR4_FETHCFG1 ((uint)0x00400000) /* PHY autoneg mode */
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#define BCSR4_FETHFDE ((uint)0x02000000) /* PHY FDX advertise */
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#define BCSR4_FETHRST ((uint)0x00200000) /* PHY Reset */
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/* IO_BASE definition for pcmcia.
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*/
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#define _IO_BASE 0x80000000
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#define _IO_BASE_SIZE 0x1000
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#ifdef CONFIG_IDE
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#define MAX_HWIFS 1
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#endif
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/* Interrupt level assignments.
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*/
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#define FEC_INTERRUPT SIU_LEVEL1 /* FEC interrupt */
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/* We don't use the 8259.
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*/
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#define NR_8259_INTS 0
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/* CPM Ethernet through SCC1 or SCC2 */
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#if defined(CONFIG_SCC1_ENET) || defined(CONFIG_MPC8xx_SECOND_ETH_SCC1) /* Probably 860 variant */
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/* Bits in parallel I/O port registers that have to be set/cleared
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* to configure the pins for SCC1 use.
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* TCLK - CLK1, RCLK - CLK2.
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*/
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#define PA_ENET_RXD ((ushort)0x0001)
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#define PA_ENET_TXD ((ushort)0x0002)
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#define PA_ENET_TCLK ((ushort)0x0100)
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#define PA_ENET_RCLK ((ushort)0x0200)
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#define PB_ENET_TENA ((uint)0x00001000)
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#define PC_ENET_CLSN ((ushort)0x0010)
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#define PC_ENET_RENA ((ushort)0x0020)
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/* Control bits in the SICR to route TCLK (CLK1) and RCLK (CLK2) to
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* SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
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*/
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#define SICR_ENET_MASK ((uint)0x000000ff)
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#define SICR_ENET_CLKRT ((uint)0x0000002c)
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#endif /* CONFIG_SCC1_ENET */
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#ifdef CONFIG_SCC2_ENET /* Probably 823/850 variant */
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/* Bits in parallel I/O port registers that have to be set/cleared
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* to configure the pins for SCC1 use.
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* TCLK - CLK1, RCLK - CLK2.
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*/
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#define PA_ENET_RXD ((ushort)0x0004)
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#define PA_ENET_TXD ((ushort)0x0008)
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#define PA_ENET_TCLK ((ushort)0x0400)
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#define PA_ENET_RCLK ((ushort)0x0200)
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#define PB_ENET_TENA ((uint)0x00002000)
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#define PC_ENET_CLSN ((ushort)0x0040)
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#define PC_ENET_RENA ((ushort)0x0080)
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/* Control bits in the SICR to route TCLK and RCLK to
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* SCC2. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
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*/
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#define SICR_ENET_MASK ((uint)0x0000ff00)
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#define SICR_ENET_CLKRT ((uint)0x00002e00)
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#endif /* CONFIG_SCC2_ENET */
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#endif /* __ASM_FADS_H__ */
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#endif /* __KERNEL__ */
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