47 lines
1.6 KiB
C
47 lines
1.6 KiB
C
/*
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* include/asm-sh/cpu-sh3/cacheflush.h
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*
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* Copyright (C) 1999 Niibe Yutaka
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#ifndef __ASM_CPU_SH3_CACHEFLUSH_H
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#define __ASM_CPU_SH3_CACHEFLUSH_H
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#if defined(CONFIG_SH7705_CACHE_32KB)
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/* SH7705 is an SH3 processor with 32KB cache. This has alias issues like the
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* SH4. Unlike the SH4 this is a unified cache so we need to do some work
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* in mmap when 'exec'ing a new binary
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*/
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/* 32KB cache, 4kb PAGE sizes need to check bit 12 */
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#define CACHE_ALIAS 0x00001000
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#define PG_mapped PG_arch_1
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void flush_cache_all(void);
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void flush_cache_mm(struct mm_struct *mm);
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#define flush_cache_dup_mm(mm) flush_cache_mm(mm)
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void flush_cache_range(struct vm_area_struct *vma, unsigned long start,
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unsigned long end);
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void flush_cache_page(struct vm_area_struct *vma, unsigned long addr, unsigned long pfn);
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void flush_dcache_page(struct page *pg);
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void flush_icache_range(unsigned long start, unsigned long end);
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void flush_icache_page(struct vm_area_struct *vma, struct page *page);
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#define flush_dcache_mmap_lock(mapping) do { } while (0)
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#define flush_dcache_mmap_unlock(mapping) do { } while (0)
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/* SH3 has unified cache so no special action needed here */
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#define flush_cache_sigtramp(vaddr) do { } while (0)
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#define flush_icache_user_range(vma,pg,adr,len) do { } while (0)
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#define p3_cache_init() do { } while (0)
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#else
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#include <cpu-common/cpu/cacheflush.h>
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#endif
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#endif /* __ASM_CPU_SH3_CACHEFLUSH_H */
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