835 lines
22 KiB
C
835 lines
22 KiB
C
/******************************************************************************
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*
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* Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
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*
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* Portions of this file are derived from the ipw3945 project, as well
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* as portions of the ieee80211 subsystem header files.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
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*
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* The full GNU General Public License is included in this distribution in the
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* file called LICENSE.
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*
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* Contact Information:
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* Intel Linux Wireless <ilw@linux.intel.com>
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* Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
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*
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*****************************************************************************/
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#include <linux/etherdevice.h>
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#include <linux/sched.h>
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#include <linux/slab.h>
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#include <net/mac80211.h>
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#include "iwl-eeprom.h"
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#include "iwl-agn.h"
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#include "iwl-dev.h"
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#include "iwl-core.h"
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#include "iwl-sta.h"
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#include "iwl-io.h"
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#include "iwl-helpers.h"
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/**
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* iwl_txq_update_write_ptr - Send new write index to hardware
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*/
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void iwl_txq_update_write_ptr(struct iwl_priv *priv, struct iwl_tx_queue *txq)
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{
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u32 reg = 0;
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int txq_id = txq->q.id;
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if (txq->need_update == 0)
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return;
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if (priv->cfg->base_params->shadow_reg_enable) {
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/* shadow register enabled */
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iwl_write32(priv, HBUS_TARG_WRPTR,
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txq->q.write_ptr | (txq_id << 8));
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} else {
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/* if we're trying to save power */
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if (test_bit(STATUS_POWER_PMI, &priv->status)) {
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/* wake up nic if it's powered down ...
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* uCode will wake up, and interrupt us again, so next
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* time we'll skip this part. */
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reg = iwl_read32(priv, CSR_UCODE_DRV_GP1);
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if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
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IWL_DEBUG_INFO(priv,
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"Tx queue %d requesting wakeup,"
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" GP1 = 0x%x\n", txq_id, reg);
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iwl_set_bit(priv, CSR_GP_CNTRL,
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CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
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return;
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}
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iwl_write_direct32(priv, HBUS_TARG_WRPTR,
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txq->q.write_ptr | (txq_id << 8));
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/*
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* else not in power-save mode,
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* uCode will never sleep when we're
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* trying to tx (during RFKILL, we're not trying to tx).
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*/
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} else
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iwl_write32(priv, HBUS_TARG_WRPTR,
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txq->q.write_ptr | (txq_id << 8));
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}
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txq->need_update = 0;
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}
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static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
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{
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struct iwl_tfd_tb *tb = &tfd->tbs[idx];
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dma_addr_t addr = get_unaligned_le32(&tb->lo);
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if (sizeof(dma_addr_t) > sizeof(u32))
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addr |=
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((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
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return addr;
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}
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static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx)
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{
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struct iwl_tfd_tb *tb = &tfd->tbs[idx];
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return le16_to_cpu(tb->hi_n_len) >> 4;
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}
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static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx,
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dma_addr_t addr, u16 len)
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{
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struct iwl_tfd_tb *tb = &tfd->tbs[idx];
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u16 hi_n_len = len << 4;
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put_unaligned_le32(addr, &tb->lo);
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if (sizeof(dma_addr_t) > sizeof(u32))
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hi_n_len |= ((addr >> 16) >> 16) & 0xF;
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tb->hi_n_len = cpu_to_le16(hi_n_len);
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tfd->num_tbs = idx + 1;
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}
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static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd)
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{
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return tfd->num_tbs & 0x1f;
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}
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static void iwlagn_unmap_tfd(struct iwl_priv *priv, struct iwl_cmd_meta *meta,
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struct iwl_tfd *tfd)
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{
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struct pci_dev *dev = priv->pci_dev;
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int i;
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int num_tbs;
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/* Sanity check on number of chunks */
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num_tbs = iwl_tfd_get_num_tbs(tfd);
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if (num_tbs >= IWL_NUM_OF_TBS) {
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IWL_ERR(priv, "Too many chunks: %i\n", num_tbs);
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/* @todo issue fatal error, it is quite serious situation */
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return;
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}
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/* Unmap tx_cmd */
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if (num_tbs)
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pci_unmap_single(dev,
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dma_unmap_addr(meta, mapping),
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dma_unmap_len(meta, len),
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PCI_DMA_BIDIRECTIONAL);
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/* Unmap chunks, if any. */
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for (i = 1; i < num_tbs; i++)
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pci_unmap_single(dev, iwl_tfd_tb_get_addr(tfd, i),
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iwl_tfd_tb_get_len(tfd, i), PCI_DMA_TODEVICE);
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}
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/**
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* iwlagn_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
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* @priv - driver private data
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* @txq - tx queue
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*
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* Does NOT advance any TFD circular buffer read/write indexes
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* Does NOT free the TFD itself (which is within circular buffer)
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*/
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void iwlagn_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
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{
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struct iwl_tfd *tfd_tmp = txq->tfds;
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int index = txq->q.read_ptr;
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iwlagn_unmap_tfd(priv, &txq->meta[index], &tfd_tmp[index]);
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/* free SKB */
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if (txq->txb) {
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struct sk_buff *skb;
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skb = txq->txb[txq->q.read_ptr].skb;
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/* can be called from irqs-disabled context */
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if (skb) {
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dev_kfree_skb_any(skb);
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txq->txb[txq->q.read_ptr].skb = NULL;
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}
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}
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}
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int iwlagn_txq_attach_buf_to_tfd(struct iwl_priv *priv,
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struct iwl_tx_queue *txq,
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dma_addr_t addr, u16 len,
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u8 reset)
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{
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struct iwl_queue *q;
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struct iwl_tfd *tfd, *tfd_tmp;
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u32 num_tbs;
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q = &txq->q;
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tfd_tmp = txq->tfds;
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tfd = &tfd_tmp[q->write_ptr];
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if (reset)
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memset(tfd, 0, sizeof(*tfd));
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num_tbs = iwl_tfd_get_num_tbs(tfd);
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/* Each TFD can point to a maximum 20 Tx buffers */
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if (num_tbs >= IWL_NUM_OF_TBS) {
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IWL_ERR(priv, "Error can not send more than %d chunks\n",
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IWL_NUM_OF_TBS);
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return -EINVAL;
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}
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if (WARN_ON(addr & ~DMA_BIT_MASK(36)))
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return -EINVAL;
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if (unlikely(addr & ~IWL_TX_DMA_MASK))
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IWL_ERR(priv, "Unaligned address = %llx\n",
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(unsigned long long)addr);
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iwl_tfd_set_tb(tfd, num_tbs, addr, len);
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return 0;
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}
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/*
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* Tell nic where to find circular buffer of Tx Frame Descriptors for
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* given Tx queue, and enable the DMA channel used for that queue.
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*
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* supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
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* channels supported in hardware.
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*/
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static int iwlagn_tx_queue_init(struct iwl_priv *priv, struct iwl_tx_queue *txq)
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{
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int txq_id = txq->q.id;
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/* Circular buffer (TFD queue in DRAM) physical base address */
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iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
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txq->q.dma_addr >> 8);
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return 0;
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}
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/**
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* iwl_tx_queue_unmap - Unmap any remaining DMA mappings and free skb's
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*/
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void iwl_tx_queue_unmap(struct iwl_priv *priv, int txq_id)
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{
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struct iwl_tx_queue *txq = &priv->txq[txq_id];
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struct iwl_queue *q = &txq->q;
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if (q->n_bd == 0)
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return;
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while (q->write_ptr != q->read_ptr) {
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iwlagn_txq_free_tfd(priv, txq);
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q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd);
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}
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}
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/**
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* iwl_tx_queue_free - Deallocate DMA queue.
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* @txq: Transmit queue to deallocate.
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*
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* Empty queue by removing and destroying all BD's.
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* Free all buffers.
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* 0-fill, but do not free "txq" descriptor structure.
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*/
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void iwl_tx_queue_free(struct iwl_priv *priv, int txq_id)
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{
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struct iwl_tx_queue *txq = &priv->txq[txq_id];
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struct device *dev = &priv->pci_dev->dev;
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int i;
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iwl_tx_queue_unmap(priv, txq_id);
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/* De-alloc array of command/tx buffers */
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for (i = 0; i < TFD_TX_CMD_SLOTS; i++)
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kfree(txq->cmd[i]);
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/* De-alloc circular buffer of TFDs */
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if (txq->q.n_bd)
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dma_free_coherent(dev, priv->hw_params.tfd_size *
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txq->q.n_bd, txq->tfds, txq->q.dma_addr);
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/* De-alloc array of per-TFD driver data */
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kfree(txq->txb);
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txq->txb = NULL;
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/* deallocate arrays */
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kfree(txq->cmd);
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kfree(txq->meta);
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txq->cmd = NULL;
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txq->meta = NULL;
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/* 0-fill queue descriptor structure */
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memset(txq, 0, sizeof(*txq));
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}
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/**
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* iwl_cmd_queue_unmap - Unmap any remaining DMA mappings from command queue
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*/
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void iwl_cmd_queue_unmap(struct iwl_priv *priv)
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{
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struct iwl_tx_queue *txq = &priv->txq[priv->cmd_queue];
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struct iwl_queue *q = &txq->q;
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int i;
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if (q->n_bd == 0)
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return;
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while (q->read_ptr != q->write_ptr) {
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i = get_cmd_index(q, q->read_ptr);
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if (txq->meta[i].flags & CMD_MAPPED) {
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pci_unmap_single(priv->pci_dev,
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dma_unmap_addr(&txq->meta[i], mapping),
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dma_unmap_len(&txq->meta[i], len),
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PCI_DMA_BIDIRECTIONAL);
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txq->meta[i].flags = 0;
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}
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q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd);
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}
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}
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/**
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* iwl_cmd_queue_free - Deallocate DMA queue.
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* @txq: Transmit queue to deallocate.
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*
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* Empty queue by removing and destroying all BD's.
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* Free all buffers.
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* 0-fill, but do not free "txq" descriptor structure.
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*/
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void iwl_cmd_queue_free(struct iwl_priv *priv)
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{
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struct iwl_tx_queue *txq = &priv->txq[priv->cmd_queue];
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struct device *dev = &priv->pci_dev->dev;
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int i;
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iwl_cmd_queue_unmap(priv);
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/* De-alloc array of command/tx buffers */
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for (i = 0; i < TFD_CMD_SLOTS; i++)
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kfree(txq->cmd[i]);
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/* De-alloc circular buffer of TFDs */
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if (txq->q.n_bd)
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dma_free_coherent(dev, priv->hw_params.tfd_size * txq->q.n_bd,
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txq->tfds, txq->q.dma_addr);
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/* deallocate arrays */
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kfree(txq->cmd);
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kfree(txq->meta);
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txq->cmd = NULL;
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txq->meta = NULL;
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/* 0-fill queue descriptor structure */
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memset(txq, 0, sizeof(*txq));
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}
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/*************** DMA-QUEUE-GENERAL-FUNCTIONS *****
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* DMA services
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*
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* Theory of operation
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*
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* A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
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* of buffer descriptors, each of which points to one or more data buffers for
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* the device to read from or fill. Driver and device exchange status of each
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* queue via "read" and "write" pointers. Driver keeps minimum of 2 empty
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* entries in each circular buffer, to protect against confusing empty and full
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* queue states.
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*
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* The device reads or writes the data in the queues via the device's several
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* DMA/FIFO channels. Each queue is mapped to a single DMA channel.
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*
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* For Tx queue, there are low mark and high mark limits. If, after queuing
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* the packet for Tx, free space become < low mark, Tx queue stopped. When
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* reclaiming packets (on 'tx done IRQ), if free space become > high mark,
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* Tx queue resumed.
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*
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***************************************************/
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int iwl_queue_space(const struct iwl_queue *q)
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{
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int s = q->read_ptr - q->write_ptr;
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if (q->read_ptr > q->write_ptr)
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s -= q->n_bd;
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if (s <= 0)
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s += q->n_window;
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/* keep some reserve to not confuse empty and full situations */
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s -= 2;
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if (s < 0)
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s = 0;
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return s;
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}
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/**
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* iwl_queue_init - Initialize queue's high/low-water and read/write indexes
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*/
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static int iwl_queue_init(struct iwl_priv *priv, struct iwl_queue *q,
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int count, int slots_num, u32 id)
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{
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q->n_bd = count;
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q->n_window = slots_num;
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q->id = id;
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/* count must be power-of-two size, otherwise iwl_queue_inc_wrap
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* and iwl_queue_dec_wrap are broken. */
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if (WARN_ON(!is_power_of_2(count)))
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return -EINVAL;
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/* slots_num must be power-of-two size, otherwise
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* get_cmd_index is broken. */
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if (WARN_ON(!is_power_of_2(slots_num)))
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return -EINVAL;
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q->low_mark = q->n_window / 4;
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if (q->low_mark < 4)
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q->low_mark = 4;
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q->high_mark = q->n_window / 8;
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if (q->high_mark < 2)
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q->high_mark = 2;
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q->write_ptr = q->read_ptr = 0;
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return 0;
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}
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/**
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* iwl_tx_queue_alloc - Alloc driver data and TFD CB for one Tx/cmd queue
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*/
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static int iwl_tx_queue_alloc(struct iwl_priv *priv,
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struct iwl_tx_queue *txq, u32 id)
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{
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struct device *dev = &priv->pci_dev->dev;
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size_t tfd_sz = priv->hw_params.tfd_size * TFD_QUEUE_SIZE_MAX;
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/* Driver private data, only for Tx (not command) queues,
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* not shared with device. */
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if (id != priv->cmd_queue) {
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txq->txb = kzalloc(sizeof(txq->txb[0]) *
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TFD_QUEUE_SIZE_MAX, GFP_KERNEL);
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if (!txq->txb) {
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IWL_ERR(priv, "kmalloc for auxiliary BD "
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"structures failed\n");
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goto error;
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}
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} else {
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txq->txb = NULL;
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}
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/* Circular buffer of transmit frame descriptors (TFDs),
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* shared with device */
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txq->tfds = dma_alloc_coherent(dev, tfd_sz, &txq->q.dma_addr,
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GFP_KERNEL);
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if (!txq->tfds) {
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IWL_ERR(priv, "pci_alloc_consistent(%zd) failed\n", tfd_sz);
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goto error;
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}
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txq->q.id = id;
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return 0;
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error:
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kfree(txq->txb);
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txq->txb = NULL;
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return -ENOMEM;
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}
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|
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/**
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* iwl_tx_queue_init - Allocate and initialize one tx/cmd queue
|
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*/
|
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int iwl_tx_queue_init(struct iwl_priv *priv, struct iwl_tx_queue *txq,
|
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int slots_num, u32 txq_id)
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{
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int i, len;
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int ret;
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|
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txq->meta = kzalloc(sizeof(struct iwl_cmd_meta) * slots_num,
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GFP_KERNEL);
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txq->cmd = kzalloc(sizeof(struct iwl_device_cmd *) * slots_num,
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GFP_KERNEL);
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|
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if (!txq->meta || !txq->cmd)
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goto out_free_arrays;
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len = sizeof(struct iwl_device_cmd);
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for (i = 0; i < slots_num; i++) {
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txq->cmd[i] = kmalloc(len, GFP_KERNEL);
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if (!txq->cmd[i])
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|
goto err;
|
|
}
|
|
|
|
/* Alloc driver data array and TFD circular buffer */
|
|
ret = iwl_tx_queue_alloc(priv, txq, txq_id);
|
|
if (ret)
|
|
goto err;
|
|
|
|
txq->need_update = 0;
|
|
|
|
/*
|
|
* For the default queues 0-3, set up the swq_id
|
|
* already -- all others need to get one later
|
|
* (if they need one at all).
|
|
*/
|
|
if (txq_id < 4)
|
|
iwl_set_swq_id(txq, txq_id, txq_id);
|
|
|
|
/* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
|
|
* iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
|
|
BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
|
|
|
|
/* Initialize queue's high/low-water marks, and head/tail indexes */
|
|
ret = iwl_queue_init(priv, &txq->q, TFD_QUEUE_SIZE_MAX, slots_num, txq_id);
|
|
if (ret)
|
|
return ret;
|
|
|
|
/* Tell device where to find queue */
|
|
iwlagn_tx_queue_init(priv, txq);
|
|
|
|
return 0;
|
|
err:
|
|
for (i = 0; i < slots_num; i++)
|
|
kfree(txq->cmd[i]);
|
|
out_free_arrays:
|
|
kfree(txq->meta);
|
|
kfree(txq->cmd);
|
|
|
|
return -ENOMEM;
|
|
}
|
|
|
|
void iwl_tx_queue_reset(struct iwl_priv *priv, struct iwl_tx_queue *txq,
|
|
int slots_num, u32 txq_id)
|
|
{
|
|
int actual_slots = slots_num;
|
|
|
|
if (txq_id == priv->cmd_queue)
|
|
actual_slots++;
|
|
|
|
memset(txq->meta, 0, sizeof(struct iwl_cmd_meta) * actual_slots);
|
|
|
|
txq->need_update = 0;
|
|
|
|
/* Initialize queue's high/low-water marks, and head/tail indexes */
|
|
iwl_queue_init(priv, &txq->q, TFD_QUEUE_SIZE_MAX, slots_num, txq_id);
|
|
|
|
/* Tell device where to find queue */
|
|
iwlagn_tx_queue_init(priv, txq);
|
|
}
|
|
|
|
/*************** HOST COMMAND QUEUE FUNCTIONS *****/
|
|
|
|
/**
|
|
* iwl_enqueue_hcmd - enqueue a uCode command
|
|
* @priv: device private data point
|
|
* @cmd: a point to the ucode command structure
|
|
*
|
|
* The function returns < 0 values to indicate the operation is
|
|
* failed. On success, it turns the index (> 0) of command in the
|
|
* command queue.
|
|
*/
|
|
int iwl_enqueue_hcmd(struct iwl_priv *priv, struct iwl_host_cmd *cmd)
|
|
{
|
|
struct iwl_tx_queue *txq = &priv->txq[priv->cmd_queue];
|
|
struct iwl_queue *q = &txq->q;
|
|
struct iwl_device_cmd *out_cmd;
|
|
struct iwl_cmd_meta *out_meta;
|
|
dma_addr_t phys_addr;
|
|
unsigned long flags;
|
|
u32 idx;
|
|
u16 copy_size, cmd_size;
|
|
bool is_ct_kill = false;
|
|
bool had_nocopy = false;
|
|
int i;
|
|
u8 *cmd_dest;
|
|
#ifdef CONFIG_IWLWIFI_DEVICE_TRACING
|
|
const void *trace_bufs[IWL_MAX_CMD_TFDS + 1] = {};
|
|
int trace_lens[IWL_MAX_CMD_TFDS + 1] = {};
|
|
int trace_idx;
|
|
#endif
|
|
|
|
if (test_bit(STATUS_FW_ERROR, &priv->status)) {
|
|
IWL_WARN(priv, "fw recovery, no hcmd send\n");
|
|
return -EIO;
|
|
}
|
|
|
|
copy_size = sizeof(out_cmd->hdr);
|
|
cmd_size = sizeof(out_cmd->hdr);
|
|
|
|
/* need one for the header if the first is NOCOPY */
|
|
BUILD_BUG_ON(IWL_MAX_CMD_TFDS > IWL_NUM_OF_TBS - 1);
|
|
|
|
for (i = 0; i < IWL_MAX_CMD_TFDS; i++) {
|
|
if (!cmd->len[i])
|
|
continue;
|
|
if (cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY) {
|
|
had_nocopy = true;
|
|
} else {
|
|
/* NOCOPY must not be followed by normal! */
|
|
if (WARN_ON(had_nocopy))
|
|
return -EINVAL;
|
|
copy_size += cmd->len[i];
|
|
}
|
|
cmd_size += cmd->len[i];
|
|
}
|
|
|
|
/*
|
|
* If any of the command structures end up being larger than
|
|
* the TFD_MAX_PAYLOAD_SIZE and they aren't dynamically
|
|
* allocated into separate TFDs, then we will need to
|
|
* increase the size of the buffers.
|
|
*/
|
|
if (WARN_ON(copy_size > TFD_MAX_PAYLOAD_SIZE))
|
|
return -EINVAL;
|
|
|
|
if (iwl_is_rfkill(priv) || iwl_is_ctkill(priv)) {
|
|
IWL_WARN(priv, "Not sending command - %s KILL\n",
|
|
iwl_is_rfkill(priv) ? "RF" : "CT");
|
|
return -EIO;
|
|
}
|
|
|
|
spin_lock_irqsave(&priv->hcmd_lock, flags);
|
|
|
|
if (iwl_queue_space(q) < ((cmd->flags & CMD_ASYNC) ? 2 : 1)) {
|
|
spin_unlock_irqrestore(&priv->hcmd_lock, flags);
|
|
|
|
IWL_ERR(priv, "No space in command queue\n");
|
|
is_ct_kill = iwl_check_for_ct_kill(priv);
|
|
if (!is_ct_kill) {
|
|
IWL_ERR(priv, "Restarting adapter due to queue full\n");
|
|
iwlagn_fw_error(priv, false);
|
|
}
|
|
return -ENOSPC;
|
|
}
|
|
|
|
idx = get_cmd_index(q, q->write_ptr);
|
|
out_cmd = txq->cmd[idx];
|
|
out_meta = &txq->meta[idx];
|
|
|
|
if (WARN_ON(out_meta->flags & CMD_MAPPED)) {
|
|
spin_unlock_irqrestore(&priv->hcmd_lock, flags);
|
|
return -ENOSPC;
|
|
}
|
|
|
|
memset(out_meta, 0, sizeof(*out_meta)); /* re-initialize to NULL */
|
|
if (cmd->flags & CMD_WANT_SKB)
|
|
out_meta->source = cmd;
|
|
if (cmd->flags & CMD_ASYNC)
|
|
out_meta->callback = cmd->callback;
|
|
|
|
/* set up the header */
|
|
|
|
out_cmd->hdr.cmd = cmd->id;
|
|
out_cmd->hdr.flags = 0;
|
|
out_cmd->hdr.sequence = cpu_to_le16(QUEUE_TO_SEQ(priv->cmd_queue) |
|
|
INDEX_TO_SEQ(q->write_ptr));
|
|
|
|
/* and copy the data that needs to be copied */
|
|
|
|
cmd_dest = &out_cmd->cmd.payload[0];
|
|
for (i = 0; i < IWL_MAX_CMD_TFDS; i++) {
|
|
if (!cmd->len[i])
|
|
continue;
|
|
if (cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY)
|
|
break;
|
|
memcpy(cmd_dest, cmd->data[i], cmd->len[i]);
|
|
cmd_dest += cmd->len[i];
|
|
}
|
|
|
|
IWL_DEBUG_HC(priv, "Sending command %s (#%x), seq: 0x%04X, "
|
|
"%d bytes at %d[%d]:%d\n",
|
|
get_cmd_string(out_cmd->hdr.cmd),
|
|
out_cmd->hdr.cmd,
|
|
le16_to_cpu(out_cmd->hdr.sequence), cmd_size,
|
|
q->write_ptr, idx, priv->cmd_queue);
|
|
|
|
phys_addr = pci_map_single(priv->pci_dev, &out_cmd->hdr,
|
|
copy_size, PCI_DMA_BIDIRECTIONAL);
|
|
if (unlikely(pci_dma_mapping_error(priv->pci_dev, phys_addr))) {
|
|
idx = -ENOMEM;
|
|
goto out;
|
|
}
|
|
|
|
dma_unmap_addr_set(out_meta, mapping, phys_addr);
|
|
dma_unmap_len_set(out_meta, len, copy_size);
|
|
|
|
iwlagn_txq_attach_buf_to_tfd(priv, txq, phys_addr, copy_size, 1);
|
|
#ifdef CONFIG_IWLWIFI_DEVICE_TRACING
|
|
trace_bufs[0] = &out_cmd->hdr;
|
|
trace_lens[0] = copy_size;
|
|
trace_idx = 1;
|
|
#endif
|
|
|
|
for (i = 0; i < IWL_MAX_CMD_TFDS; i++) {
|
|
if (!cmd->len[i])
|
|
continue;
|
|
if (!(cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY))
|
|
continue;
|
|
phys_addr = pci_map_single(priv->pci_dev, (void *)cmd->data[i],
|
|
cmd->len[i], PCI_DMA_TODEVICE);
|
|
if (pci_dma_mapping_error(priv->pci_dev, phys_addr)) {
|
|
iwlagn_unmap_tfd(priv, out_meta,
|
|
&txq->tfds[q->write_ptr]);
|
|
idx = -ENOMEM;
|
|
goto out;
|
|
}
|
|
|
|
iwlagn_txq_attach_buf_to_tfd(priv, txq, phys_addr,
|
|
cmd->len[i], 0);
|
|
#ifdef CONFIG_IWLWIFI_DEVICE_TRACING
|
|
trace_bufs[trace_idx] = cmd->data[i];
|
|
trace_lens[trace_idx] = cmd->len[i];
|
|
trace_idx++;
|
|
#endif
|
|
}
|
|
|
|
out_meta->flags = cmd->flags | CMD_MAPPED;
|
|
|
|
txq->need_update = 1;
|
|
|
|
/* check that tracing gets all possible blocks */
|
|
BUILD_BUG_ON(IWL_MAX_CMD_TFDS + 1 != 3);
|
|
#ifdef CONFIG_IWLWIFI_DEVICE_TRACING
|
|
trace_iwlwifi_dev_hcmd(priv, cmd->flags,
|
|
trace_bufs[0], trace_lens[0],
|
|
trace_bufs[1], trace_lens[1],
|
|
trace_bufs[2], trace_lens[2]);
|
|
#endif
|
|
|
|
/* Increment and update queue's write index */
|
|
q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
|
|
iwl_txq_update_write_ptr(priv, txq);
|
|
|
|
out:
|
|
spin_unlock_irqrestore(&priv->hcmd_lock, flags);
|
|
return idx;
|
|
}
|
|
|
|
/**
|
|
* iwl_hcmd_queue_reclaim - Reclaim TX command queue entries already Tx'd
|
|
*
|
|
* When FW advances 'R' index, all entries between old and new 'R' index
|
|
* need to be reclaimed. As result, some free space forms. If there is
|
|
* enough free space (> low mark), wake the stack that feeds us.
|
|
*/
|
|
static void iwl_hcmd_queue_reclaim(struct iwl_priv *priv, int txq_id, int idx)
|
|
{
|
|
struct iwl_tx_queue *txq = &priv->txq[txq_id];
|
|
struct iwl_queue *q = &txq->q;
|
|
int nfreed = 0;
|
|
|
|
if ((idx >= q->n_bd) || (iwl_queue_used(q, idx) == 0)) {
|
|
IWL_ERR(priv, "Read index for DMA queue txq id (%d), index %d, "
|
|
"is out of range [0-%d] %d %d.\n", txq_id,
|
|
idx, q->n_bd, q->write_ptr, q->read_ptr);
|
|
return;
|
|
}
|
|
|
|
for (idx = iwl_queue_inc_wrap(idx, q->n_bd); q->read_ptr != idx;
|
|
q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
|
|
|
|
if (nfreed++ > 0) {
|
|
IWL_ERR(priv, "HCMD skipped: index (%d) %d %d\n", idx,
|
|
q->write_ptr, q->read_ptr);
|
|
iwlagn_fw_error(priv, false);
|
|
}
|
|
|
|
}
|
|
}
|
|
|
|
/**
|
|
* iwl_tx_cmd_complete - Pull unused buffers off the queue and reclaim them
|
|
* @rxb: Rx buffer to reclaim
|
|
*
|
|
* If an Rx buffer has an async callback associated with it the callback
|
|
* will be executed. The attached skb (if present) will only be freed
|
|
* if the callback returns 1
|
|
*/
|
|
void iwl_tx_cmd_complete(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb)
|
|
{
|
|
struct iwl_rx_packet *pkt = rxb_addr(rxb);
|
|
u16 sequence = le16_to_cpu(pkt->hdr.sequence);
|
|
int txq_id = SEQ_TO_QUEUE(sequence);
|
|
int index = SEQ_TO_INDEX(sequence);
|
|
int cmd_index;
|
|
struct iwl_device_cmd *cmd;
|
|
struct iwl_cmd_meta *meta;
|
|
struct iwl_tx_queue *txq = &priv->txq[priv->cmd_queue];
|
|
unsigned long flags;
|
|
|
|
/* If a Tx command is being handled and it isn't in the actual
|
|
* command queue then there a command routing bug has been introduced
|
|
* in the queue management code. */
|
|
if (WARN(txq_id != priv->cmd_queue,
|
|
"wrong command queue %d (should be %d), sequence 0x%X readp=%d writep=%d\n",
|
|
txq_id, priv->cmd_queue, sequence,
|
|
priv->txq[priv->cmd_queue].q.read_ptr,
|
|
priv->txq[priv->cmd_queue].q.write_ptr)) {
|
|
iwl_print_hex_error(priv, pkt, 32);
|
|
return;
|
|
}
|
|
|
|
cmd_index = get_cmd_index(&txq->q, index);
|
|
cmd = txq->cmd[cmd_index];
|
|
meta = &txq->meta[cmd_index];
|
|
|
|
iwlagn_unmap_tfd(priv, meta, &txq->tfds[index]);
|
|
|
|
/* Input error checking is done when commands are added to queue. */
|
|
if (meta->flags & CMD_WANT_SKB) {
|
|
meta->source->reply_page = (unsigned long)rxb_addr(rxb);
|
|
rxb->page = NULL;
|
|
} else if (meta->callback)
|
|
meta->callback(priv, cmd, pkt);
|
|
|
|
spin_lock_irqsave(&priv->hcmd_lock, flags);
|
|
|
|
iwl_hcmd_queue_reclaim(priv, txq_id, index);
|
|
|
|
if (!(meta->flags & CMD_ASYNC)) {
|
|
clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
|
|
IWL_DEBUG_INFO(priv, "Clearing HCMD_ACTIVE for command %s\n",
|
|
get_cmd_string(cmd->hdr.cmd));
|
|
wake_up_interruptible(&priv->wait_command_queue);
|
|
}
|
|
|
|
/* Mark as unmapped */
|
|
meta->flags = 0;
|
|
|
|
spin_unlock_irqrestore(&priv->hcmd_lock, flags);
|
|
}
|