773 lines
20 KiB
C
773 lines
20 KiB
C
/*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, version 2, as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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*
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* Copyright IBM Corp. 2007
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*
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* Authors: Hollis Blanchard <hollisb@us.ibm.com>
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*/
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#include <linux/jiffies.h>
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#include <linux/timer.h>
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#include <linux/types.h>
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#include <linux/string.h>
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#include <linux/kvm_host.h>
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#include <asm/dcr.h>
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#include <asm/dcr-regs.h>
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#include <asm/time.h>
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#include <asm/byteorder.h>
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#include <asm/kvm_ppc.h>
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#include "44x_tlb.h"
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/* Instruction decoding */
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static inline unsigned int get_op(u32 inst)
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{
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return inst >> 26;
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}
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static inline unsigned int get_xop(u32 inst)
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{
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return (inst >> 1) & 0x3ff;
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}
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static inline unsigned int get_sprn(u32 inst)
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{
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return ((inst >> 16) & 0x1f) | ((inst >> 6) & 0x3e0);
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}
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static inline unsigned int get_dcrn(u32 inst)
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{
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return ((inst >> 16) & 0x1f) | ((inst >> 6) & 0x3e0);
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}
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static inline unsigned int get_rt(u32 inst)
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{
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return (inst >> 21) & 0x1f;
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}
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static inline unsigned int get_rs(u32 inst)
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{
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return (inst >> 21) & 0x1f;
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}
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static inline unsigned int get_ra(u32 inst)
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{
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return (inst >> 16) & 0x1f;
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}
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static inline unsigned int get_rb(u32 inst)
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{
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return (inst >> 11) & 0x1f;
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}
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static inline unsigned int get_rc(u32 inst)
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{
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return inst & 0x1;
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}
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static inline unsigned int get_ws(u32 inst)
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{
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return (inst >> 11) & 0x1f;
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}
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static inline unsigned int get_d(u32 inst)
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{
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return inst & 0xffff;
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}
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static int tlbe_is_host_safe(const struct kvm_vcpu *vcpu,
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const struct tlbe *tlbe)
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{
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gpa_t gpa;
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if (!get_tlb_v(tlbe))
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return 0;
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/* Does it match current guest AS? */
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/* XXX what about IS != DS? */
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if (get_tlb_ts(tlbe) != !!(vcpu->arch.msr & MSR_IS))
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return 0;
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gpa = get_tlb_raddr(tlbe);
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if (!gfn_to_memslot(vcpu->kvm, gpa >> PAGE_SHIFT))
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/* Mapping is not for RAM. */
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return 0;
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return 1;
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}
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static int kvmppc_emul_tlbwe(struct kvm_vcpu *vcpu, u32 inst)
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{
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u64 eaddr;
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u64 raddr;
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u64 asid;
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u32 flags;
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struct tlbe *tlbe;
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unsigned int ra;
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unsigned int rs;
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unsigned int ws;
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unsigned int index;
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ra = get_ra(inst);
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rs = get_rs(inst);
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ws = get_ws(inst);
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index = vcpu->arch.gpr[ra];
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if (index > PPC44x_TLB_SIZE) {
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printk("%s: index %d\n", __func__, index);
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kvmppc_dump_vcpu(vcpu);
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return EMULATE_FAIL;
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}
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tlbe = &vcpu->arch.guest_tlb[index];
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/* Invalidate shadow mappings for the about-to-be-clobbered TLBE. */
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if (tlbe->word0 & PPC44x_TLB_VALID) {
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eaddr = get_tlb_eaddr(tlbe);
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asid = (tlbe->word0 & PPC44x_TLB_TS) | tlbe->tid;
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kvmppc_mmu_invalidate(vcpu, eaddr, get_tlb_end(tlbe), asid);
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}
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switch (ws) {
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case PPC44x_TLB_PAGEID:
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tlbe->tid = vcpu->arch.mmucr & 0xff;
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tlbe->word0 = vcpu->arch.gpr[rs];
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break;
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case PPC44x_TLB_XLAT:
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tlbe->word1 = vcpu->arch.gpr[rs];
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break;
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case PPC44x_TLB_ATTRIB:
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tlbe->word2 = vcpu->arch.gpr[rs];
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break;
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default:
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return EMULATE_FAIL;
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}
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if (tlbe_is_host_safe(vcpu, tlbe)) {
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eaddr = get_tlb_eaddr(tlbe);
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raddr = get_tlb_raddr(tlbe);
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asid = (tlbe->word0 & PPC44x_TLB_TS) | tlbe->tid;
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flags = tlbe->word2 & 0xffff;
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/* Create a 4KB mapping on the host. If the guest wanted a
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* large page, only the first 4KB is mapped here and the rest
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* are mapped on the fly. */
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kvmppc_mmu_map(vcpu, eaddr, raddr >> PAGE_SHIFT, asid, flags);
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}
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return EMULATE_DONE;
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}
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static void kvmppc_emulate_dec(struct kvm_vcpu *vcpu)
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{
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if (vcpu->arch.tcr & TCR_DIE) {
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/* The decrementer ticks at the same rate as the timebase, so
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* that's how we convert the guest DEC value to the number of
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* host ticks. */
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unsigned long nr_jiffies;
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nr_jiffies = vcpu->arch.dec / tb_ticks_per_jiffy;
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mod_timer(&vcpu->arch.dec_timer,
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get_jiffies_64() + nr_jiffies);
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} else {
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del_timer(&vcpu->arch.dec_timer);
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}
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}
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static void kvmppc_emul_rfi(struct kvm_vcpu *vcpu)
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{
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vcpu->arch.pc = vcpu->arch.srr0;
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kvmppc_set_msr(vcpu, vcpu->arch.srr1);
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}
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/* XXX to do:
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* lhax
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* lhaux
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* lswx
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* lswi
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* stswx
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* stswi
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* lha
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* lhau
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* lmw
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* stmw
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*
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* XXX is_bigendian should depend on MMU mapping or MSR[LE]
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*/
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int kvmppc_emulate_instruction(struct kvm_run *run, struct kvm_vcpu *vcpu)
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{
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u32 inst = vcpu->arch.last_inst;
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u32 ea;
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int ra;
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int rb;
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int rc;
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int rs;
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int rt;
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int sprn;
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int dcrn;
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enum emulation_result emulated = EMULATE_DONE;
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int advance = 1;
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switch (get_op(inst)) {
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case 3: /* trap */
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printk("trap!\n");
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kvmppc_queue_exception(vcpu, BOOKE_INTERRUPT_PROGRAM);
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advance = 0;
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break;
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case 19:
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switch (get_xop(inst)) {
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case 50: /* rfi */
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kvmppc_emul_rfi(vcpu);
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advance = 0;
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break;
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default:
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emulated = EMULATE_FAIL;
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break;
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}
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break;
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case 31:
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switch (get_xop(inst)) {
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case 23: /* lwzx */
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rt = get_rt(inst);
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emulated = kvmppc_handle_load(run, vcpu, rt, 4, 1);
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break;
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case 83: /* mfmsr */
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rt = get_rt(inst);
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vcpu->arch.gpr[rt] = vcpu->arch.msr;
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break;
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case 87: /* lbzx */
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rt = get_rt(inst);
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emulated = kvmppc_handle_load(run, vcpu, rt, 1, 1);
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break;
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case 131: /* wrtee */
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rs = get_rs(inst);
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vcpu->arch.msr = (vcpu->arch.msr & ~MSR_EE)
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| (vcpu->arch.gpr[rs] & MSR_EE);
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break;
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case 146: /* mtmsr */
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rs = get_rs(inst);
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kvmppc_set_msr(vcpu, vcpu->arch.gpr[rs]);
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break;
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case 151: /* stwx */
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rs = get_rs(inst);
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emulated = kvmppc_handle_store(run, vcpu,
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vcpu->arch.gpr[rs],
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4, 1);
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break;
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case 163: /* wrteei */
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vcpu->arch.msr = (vcpu->arch.msr & ~MSR_EE)
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| (inst & MSR_EE);
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break;
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case 215: /* stbx */
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rs = get_rs(inst);
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emulated = kvmppc_handle_store(run, vcpu,
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vcpu->arch.gpr[rs],
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1, 1);
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break;
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case 247: /* stbux */
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rs = get_rs(inst);
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ra = get_ra(inst);
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rb = get_rb(inst);
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ea = vcpu->arch.gpr[rb];
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if (ra)
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ea += vcpu->arch.gpr[ra];
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emulated = kvmppc_handle_store(run, vcpu,
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vcpu->arch.gpr[rs],
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1, 1);
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vcpu->arch.gpr[rs] = ea;
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break;
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case 279: /* lhzx */
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rt = get_rt(inst);
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emulated = kvmppc_handle_load(run, vcpu, rt, 2, 1);
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break;
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case 311: /* lhzux */
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rt = get_rt(inst);
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ra = get_ra(inst);
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rb = get_rb(inst);
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ea = vcpu->arch.gpr[rb];
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if (ra)
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ea += vcpu->arch.gpr[ra];
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emulated = kvmppc_handle_load(run, vcpu, rt, 2, 1);
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vcpu->arch.gpr[ra] = ea;
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break;
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case 323: /* mfdcr */
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dcrn = get_dcrn(inst);
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rt = get_rt(inst);
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/* The guest may access CPR0 registers to determine the timebase
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* frequency, and it must know the real host frequency because it
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* can directly access the timebase registers.
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*
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* It would be possible to emulate those accesses in userspace,
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* but userspace can really only figure out the end frequency.
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* We could decompose that into the factors that compute it, but
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* that's tricky math, and it's easier to just report the real
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* CPR0 values.
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*/
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switch (dcrn) {
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case DCRN_CPR0_CONFIG_ADDR:
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vcpu->arch.gpr[rt] = vcpu->arch.cpr0_cfgaddr;
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break;
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case DCRN_CPR0_CONFIG_DATA:
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local_irq_disable();
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mtdcr(DCRN_CPR0_CONFIG_ADDR,
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vcpu->arch.cpr0_cfgaddr);
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vcpu->arch.gpr[rt] = mfdcr(DCRN_CPR0_CONFIG_DATA);
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local_irq_enable();
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break;
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default:
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run->dcr.dcrn = dcrn;
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run->dcr.data = 0;
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run->dcr.is_write = 0;
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vcpu->arch.io_gpr = rt;
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vcpu->arch.dcr_needed = 1;
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emulated = EMULATE_DO_DCR;
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}
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break;
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case 339: /* mfspr */
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sprn = get_sprn(inst);
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rt = get_rt(inst);
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switch (sprn) {
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case SPRN_SRR0:
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vcpu->arch.gpr[rt] = vcpu->arch.srr0; break;
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case SPRN_SRR1:
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vcpu->arch.gpr[rt] = vcpu->arch.srr1; break;
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case SPRN_MMUCR:
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vcpu->arch.gpr[rt] = vcpu->arch.mmucr; break;
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case SPRN_PID:
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vcpu->arch.gpr[rt] = vcpu->arch.pid; break;
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case SPRN_IVPR:
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vcpu->arch.gpr[rt] = vcpu->arch.ivpr; break;
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case SPRN_CCR0:
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vcpu->arch.gpr[rt] = vcpu->arch.ccr0; break;
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case SPRN_CCR1:
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vcpu->arch.gpr[rt] = vcpu->arch.ccr1; break;
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case SPRN_PVR:
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vcpu->arch.gpr[rt] = vcpu->arch.pvr; break;
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case SPRN_DEAR:
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vcpu->arch.gpr[rt] = vcpu->arch.dear; break;
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case SPRN_ESR:
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vcpu->arch.gpr[rt] = vcpu->arch.esr; break;
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case SPRN_DBCR0:
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vcpu->arch.gpr[rt] = vcpu->arch.dbcr0; break;
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case SPRN_DBCR1:
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vcpu->arch.gpr[rt] = vcpu->arch.dbcr1; break;
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/* Note: mftb and TBRL/TBWL are user-accessible, so
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* the guest can always access the real TB anyways.
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* In fact, we probably will never see these traps. */
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case SPRN_TBWL:
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vcpu->arch.gpr[rt] = mftbl(); break;
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case SPRN_TBWU:
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vcpu->arch.gpr[rt] = mftbu(); break;
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case SPRN_SPRG0:
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vcpu->arch.gpr[rt] = vcpu->arch.sprg0; break;
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case SPRN_SPRG1:
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vcpu->arch.gpr[rt] = vcpu->arch.sprg1; break;
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case SPRN_SPRG2:
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vcpu->arch.gpr[rt] = vcpu->arch.sprg2; break;
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case SPRN_SPRG3:
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vcpu->arch.gpr[rt] = vcpu->arch.sprg3; break;
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/* Note: SPRG4-7 are user-readable, so we don't get
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* a trap. */
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case SPRN_IVOR0:
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vcpu->arch.gpr[rt] = vcpu->arch.ivor[0]; break;
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case SPRN_IVOR1:
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vcpu->arch.gpr[rt] = vcpu->arch.ivor[1]; break;
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case SPRN_IVOR2:
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vcpu->arch.gpr[rt] = vcpu->arch.ivor[2]; break;
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case SPRN_IVOR3:
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vcpu->arch.gpr[rt] = vcpu->arch.ivor[3]; break;
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case SPRN_IVOR4:
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vcpu->arch.gpr[rt] = vcpu->arch.ivor[4]; break;
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case SPRN_IVOR5:
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vcpu->arch.gpr[rt] = vcpu->arch.ivor[5]; break;
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case SPRN_IVOR6:
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vcpu->arch.gpr[rt] = vcpu->arch.ivor[6]; break;
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case SPRN_IVOR7:
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vcpu->arch.gpr[rt] = vcpu->arch.ivor[7]; break;
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case SPRN_IVOR8:
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vcpu->arch.gpr[rt] = vcpu->arch.ivor[8]; break;
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case SPRN_IVOR9:
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vcpu->arch.gpr[rt] = vcpu->arch.ivor[9]; break;
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case SPRN_IVOR10:
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vcpu->arch.gpr[rt] = vcpu->arch.ivor[10]; break;
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case SPRN_IVOR11:
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vcpu->arch.gpr[rt] = vcpu->arch.ivor[11]; break;
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case SPRN_IVOR12:
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vcpu->arch.gpr[rt] = vcpu->arch.ivor[12]; break;
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case SPRN_IVOR13:
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vcpu->arch.gpr[rt] = vcpu->arch.ivor[13]; break;
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case SPRN_IVOR14:
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vcpu->arch.gpr[rt] = vcpu->arch.ivor[14]; break;
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case SPRN_IVOR15:
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vcpu->arch.gpr[rt] = vcpu->arch.ivor[15]; break;
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default:
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printk("mfspr: unknown spr %x\n", sprn);
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vcpu->arch.gpr[rt] = 0;
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break;
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}
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break;
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case 407: /* sthx */
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rs = get_rs(inst);
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ra = get_ra(inst);
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rb = get_rb(inst);
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emulated = kvmppc_handle_store(run, vcpu,
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vcpu->arch.gpr[rs],
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2, 1);
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break;
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case 439: /* sthux */
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rs = get_rs(inst);
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ra = get_ra(inst);
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rb = get_rb(inst);
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ea = vcpu->arch.gpr[rb];
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if (ra)
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ea += vcpu->arch.gpr[ra];
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emulated = kvmppc_handle_store(run, vcpu,
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vcpu->arch.gpr[rs],
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2, 1);
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vcpu->arch.gpr[ra] = ea;
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break;
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case 451: /* mtdcr */
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dcrn = get_dcrn(inst);
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rs = get_rs(inst);
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/* emulate some access in kernel */
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switch (dcrn) {
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case DCRN_CPR0_CONFIG_ADDR:
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vcpu->arch.cpr0_cfgaddr = vcpu->arch.gpr[rs];
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break;
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default:
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run->dcr.dcrn = dcrn;
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run->dcr.data = vcpu->arch.gpr[rs];
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run->dcr.is_write = 1;
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vcpu->arch.dcr_needed = 1;
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emulated = EMULATE_DO_DCR;
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}
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break;
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case 467: /* mtspr */
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sprn = get_sprn(inst);
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rs = get_rs(inst);
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switch (sprn) {
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case SPRN_SRR0:
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vcpu->arch.srr0 = vcpu->arch.gpr[rs]; break;
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case SPRN_SRR1:
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vcpu->arch.srr1 = vcpu->arch.gpr[rs]; break;
|
|
case SPRN_MMUCR:
|
|
vcpu->arch.mmucr = vcpu->arch.gpr[rs]; break;
|
|
case SPRN_PID:
|
|
vcpu->arch.pid = vcpu->arch.gpr[rs]; break;
|
|
case SPRN_CCR0:
|
|
vcpu->arch.ccr0 = vcpu->arch.gpr[rs]; break;
|
|
case SPRN_CCR1:
|
|
vcpu->arch.ccr1 = vcpu->arch.gpr[rs]; break;
|
|
case SPRN_DEAR:
|
|
vcpu->arch.dear = vcpu->arch.gpr[rs]; break;
|
|
case SPRN_ESR:
|
|
vcpu->arch.esr = vcpu->arch.gpr[rs]; break;
|
|
case SPRN_DBCR0:
|
|
vcpu->arch.dbcr0 = vcpu->arch.gpr[rs]; break;
|
|
case SPRN_DBCR1:
|
|
vcpu->arch.dbcr1 = vcpu->arch.gpr[rs]; break;
|
|
|
|
/* XXX We need to context-switch the timebase for
|
|
* watchdog and FIT. */
|
|
case SPRN_TBWL: break;
|
|
case SPRN_TBWU: break;
|
|
|
|
case SPRN_DEC:
|
|
vcpu->arch.dec = vcpu->arch.gpr[rs];
|
|
kvmppc_emulate_dec(vcpu);
|
|
break;
|
|
|
|
case SPRN_TSR:
|
|
vcpu->arch.tsr &= ~vcpu->arch.gpr[rs]; break;
|
|
|
|
case SPRN_TCR:
|
|
vcpu->arch.tcr = vcpu->arch.gpr[rs];
|
|
kvmppc_emulate_dec(vcpu);
|
|
break;
|
|
|
|
case SPRN_SPRG0:
|
|
vcpu->arch.sprg0 = vcpu->arch.gpr[rs]; break;
|
|
case SPRN_SPRG1:
|
|
vcpu->arch.sprg1 = vcpu->arch.gpr[rs]; break;
|
|
case SPRN_SPRG2:
|
|
vcpu->arch.sprg2 = vcpu->arch.gpr[rs]; break;
|
|
case SPRN_SPRG3:
|
|
vcpu->arch.sprg3 = vcpu->arch.gpr[rs]; break;
|
|
|
|
/* Note: SPRG4-7 are user-readable. These values are
|
|
* loaded into the real SPRGs when resuming the
|
|
* guest. */
|
|
case SPRN_SPRG4:
|
|
vcpu->arch.sprg4 = vcpu->arch.gpr[rs]; break;
|
|
case SPRN_SPRG5:
|
|
vcpu->arch.sprg5 = vcpu->arch.gpr[rs]; break;
|
|
case SPRN_SPRG6:
|
|
vcpu->arch.sprg6 = vcpu->arch.gpr[rs]; break;
|
|
case SPRN_SPRG7:
|
|
vcpu->arch.sprg7 = vcpu->arch.gpr[rs]; break;
|
|
|
|
case SPRN_IVPR:
|
|
vcpu->arch.ivpr = vcpu->arch.gpr[rs]; break;
|
|
case SPRN_IVOR0:
|
|
vcpu->arch.ivor[0] = vcpu->arch.gpr[rs]; break;
|
|
case SPRN_IVOR1:
|
|
vcpu->arch.ivor[1] = vcpu->arch.gpr[rs]; break;
|
|
case SPRN_IVOR2:
|
|
vcpu->arch.ivor[2] = vcpu->arch.gpr[rs]; break;
|
|
case SPRN_IVOR3:
|
|
vcpu->arch.ivor[3] = vcpu->arch.gpr[rs]; break;
|
|
case SPRN_IVOR4:
|
|
vcpu->arch.ivor[4] = vcpu->arch.gpr[rs]; break;
|
|
case SPRN_IVOR5:
|
|
vcpu->arch.ivor[5] = vcpu->arch.gpr[rs]; break;
|
|
case SPRN_IVOR6:
|
|
vcpu->arch.ivor[6] = vcpu->arch.gpr[rs]; break;
|
|
case SPRN_IVOR7:
|
|
vcpu->arch.ivor[7] = vcpu->arch.gpr[rs]; break;
|
|
case SPRN_IVOR8:
|
|
vcpu->arch.ivor[8] = vcpu->arch.gpr[rs]; break;
|
|
case SPRN_IVOR9:
|
|
vcpu->arch.ivor[9] = vcpu->arch.gpr[rs]; break;
|
|
case SPRN_IVOR10:
|
|
vcpu->arch.ivor[10] = vcpu->arch.gpr[rs]; break;
|
|
case SPRN_IVOR11:
|
|
vcpu->arch.ivor[11] = vcpu->arch.gpr[rs]; break;
|
|
case SPRN_IVOR12:
|
|
vcpu->arch.ivor[12] = vcpu->arch.gpr[rs]; break;
|
|
case SPRN_IVOR13:
|
|
vcpu->arch.ivor[13] = vcpu->arch.gpr[rs]; break;
|
|
case SPRN_IVOR14:
|
|
vcpu->arch.ivor[14] = vcpu->arch.gpr[rs]; break;
|
|
case SPRN_IVOR15:
|
|
vcpu->arch.ivor[15] = vcpu->arch.gpr[rs]; break;
|
|
|
|
default:
|
|
printk("mtspr: unknown spr %x\n", sprn);
|
|
emulated = EMULATE_FAIL;
|
|
break;
|
|
}
|
|
break;
|
|
|
|
case 470: /* dcbi */
|
|
/* Do nothing. The guest is performing dcbi because
|
|
* hardware DMA is not snooped by the dcache, but
|
|
* emulated DMA either goes through the dcache as
|
|
* normal writes, or the host kernel has handled dcache
|
|
* coherence. */
|
|
break;
|
|
|
|
case 534: /* lwbrx */
|
|
rt = get_rt(inst);
|
|
emulated = kvmppc_handle_load(run, vcpu, rt, 4, 0);
|
|
break;
|
|
|
|
case 566: /* tlbsync */
|
|
break;
|
|
|
|
case 662: /* stwbrx */
|
|
rs = get_rs(inst);
|
|
ra = get_ra(inst);
|
|
rb = get_rb(inst);
|
|
|
|
emulated = kvmppc_handle_store(run, vcpu,
|
|
vcpu->arch.gpr[rs],
|
|
4, 0);
|
|
break;
|
|
|
|
case 978: /* tlbwe */
|
|
emulated = kvmppc_emul_tlbwe(vcpu, inst);
|
|
break;
|
|
|
|
case 914: { /* tlbsx */
|
|
int index;
|
|
unsigned int as = get_mmucr_sts(vcpu);
|
|
unsigned int pid = get_mmucr_stid(vcpu);
|
|
|
|
rt = get_rt(inst);
|
|
ra = get_ra(inst);
|
|
rb = get_rb(inst);
|
|
rc = get_rc(inst);
|
|
|
|
ea = vcpu->arch.gpr[rb];
|
|
if (ra)
|
|
ea += vcpu->arch.gpr[ra];
|
|
|
|
index = kvmppc_44x_tlb_index(vcpu, ea, pid, as);
|
|
if (rc) {
|
|
if (index < 0)
|
|
vcpu->arch.cr &= ~0x20000000;
|
|
else
|
|
vcpu->arch.cr |= 0x20000000;
|
|
}
|
|
vcpu->arch.gpr[rt] = index;
|
|
|
|
}
|
|
break;
|
|
|
|
case 790: /* lhbrx */
|
|
rt = get_rt(inst);
|
|
emulated = kvmppc_handle_load(run, vcpu, rt, 2, 0);
|
|
break;
|
|
|
|
case 918: /* sthbrx */
|
|
rs = get_rs(inst);
|
|
ra = get_ra(inst);
|
|
rb = get_rb(inst);
|
|
|
|
emulated = kvmppc_handle_store(run, vcpu,
|
|
vcpu->arch.gpr[rs],
|
|
2, 0);
|
|
break;
|
|
|
|
case 966: /* iccci */
|
|
break;
|
|
|
|
default:
|
|
printk("unknown: op %d xop %d\n", get_op(inst),
|
|
get_xop(inst));
|
|
emulated = EMULATE_FAIL;
|
|
break;
|
|
}
|
|
break;
|
|
|
|
case 32: /* lwz */
|
|
rt = get_rt(inst);
|
|
emulated = kvmppc_handle_load(run, vcpu, rt, 4, 1);
|
|
break;
|
|
|
|
case 33: /* lwzu */
|
|
ra = get_ra(inst);
|
|
rt = get_rt(inst);
|
|
emulated = kvmppc_handle_load(run, vcpu, rt, 4, 1);
|
|
vcpu->arch.gpr[ra] = vcpu->arch.paddr_accessed;
|
|
break;
|
|
|
|
case 34: /* lbz */
|
|
rt = get_rt(inst);
|
|
emulated = kvmppc_handle_load(run, vcpu, rt, 1, 1);
|
|
break;
|
|
|
|
case 35: /* lbzu */
|
|
ra = get_ra(inst);
|
|
rt = get_rt(inst);
|
|
emulated = kvmppc_handle_load(run, vcpu, rt, 1, 1);
|
|
vcpu->arch.gpr[ra] = vcpu->arch.paddr_accessed;
|
|
break;
|
|
|
|
case 36: /* stw */
|
|
rs = get_rs(inst);
|
|
emulated = kvmppc_handle_store(run, vcpu, vcpu->arch.gpr[rs],
|
|
4, 1);
|
|
break;
|
|
|
|
case 37: /* stwu */
|
|
ra = get_ra(inst);
|
|
rs = get_rs(inst);
|
|
emulated = kvmppc_handle_store(run, vcpu, vcpu->arch.gpr[rs],
|
|
4, 1);
|
|
vcpu->arch.gpr[ra] = vcpu->arch.paddr_accessed;
|
|
break;
|
|
|
|
case 38: /* stb */
|
|
rs = get_rs(inst);
|
|
emulated = kvmppc_handle_store(run, vcpu, vcpu->arch.gpr[rs],
|
|
1, 1);
|
|
break;
|
|
|
|
case 39: /* stbu */
|
|
ra = get_ra(inst);
|
|
rs = get_rs(inst);
|
|
emulated = kvmppc_handle_store(run, vcpu, vcpu->arch.gpr[rs],
|
|
1, 1);
|
|
vcpu->arch.gpr[ra] = vcpu->arch.paddr_accessed;
|
|
break;
|
|
|
|
case 40: /* lhz */
|
|
rt = get_rt(inst);
|
|
emulated = kvmppc_handle_load(run, vcpu, rt, 2, 1);
|
|
break;
|
|
|
|
case 41: /* lhzu */
|
|
ra = get_ra(inst);
|
|
rt = get_rt(inst);
|
|
emulated = kvmppc_handle_load(run, vcpu, rt, 2, 1);
|
|
vcpu->arch.gpr[ra] = vcpu->arch.paddr_accessed;
|
|
break;
|
|
|
|
case 44: /* sth */
|
|
rs = get_rs(inst);
|
|
emulated = kvmppc_handle_store(run, vcpu, vcpu->arch.gpr[rs],
|
|
2, 1);
|
|
break;
|
|
|
|
case 45: /* sthu */
|
|
ra = get_ra(inst);
|
|
rs = get_rs(inst);
|
|
emulated = kvmppc_handle_store(run, vcpu, vcpu->arch.gpr[rs],
|
|
2, 1);
|
|
vcpu->arch.gpr[ra] = vcpu->arch.paddr_accessed;
|
|
break;
|
|
|
|
default:
|
|
printk("unknown op %d\n", get_op(inst));
|
|
emulated = EMULATE_FAIL;
|
|
break;
|
|
}
|
|
|
|
if (advance)
|
|
vcpu->arch.pc += 4; /* Advance past emulated instruction. */
|
|
|
|
return emulated;
|
|
}
|