975 lines
25 KiB
C
975 lines
25 KiB
C
/*
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* ETRAX CRISv32 general port I/O device
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*
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* Copyright (c) 1999-2006 Axis Communications AB
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*
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* Authors: Bjorn Wesen (initial version)
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* Ola Knutsson (LED handling)
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* Johan Adolfsson (read/set directions, write, port G,
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* port to ETRAX FS.
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*
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*/
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#include <linux/module.h>
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#include <linux/sched.h>
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#include <linux/slab.h>
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#include <linux/ioport.h>
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#include <linux/errno.h>
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#include <linux/kernel.h>
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#include <linux/fs.h>
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#include <linux/string.h>
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#include <linux/poll.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/spinlock.h>
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#include <linux/smp_lock.h>
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#include <asm/etraxgpio.h>
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#include <hwregs/reg_map.h>
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#include <hwregs/reg_rdwr.h>
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#include <hwregs/gio_defs.h>
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#include <hwregs/intr_vect_defs.h>
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#include <asm/io.h>
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#include <asm/system.h>
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#include <asm/irq.h>
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#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
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#include "../i2c.h"
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#define VIRT_I2C_ADDR 0x40
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#endif
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/* The following gio ports on ETRAX FS is available:
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* pa 8 bits, supports interrupts off, hi, low, set, posedge, negedge anyedge
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* pb 18 bits
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* pc 18 bits
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* pd 18 bits
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* pe 18 bits
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* each port has a rw_px_dout, r_px_din and rw_px_oe register.
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*/
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#define GPIO_MAJOR 120 /* experimental MAJOR number */
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#define D(x)
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#if 0
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static int dp_cnt;
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#define DP(x) \
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do { \
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dp_cnt++; \
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if (dp_cnt % 1000 == 0) \
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x; \
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} while (0)
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#else
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#define DP(x)
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#endif
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static char gpio_name[] = "etrax gpio";
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#if 0
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static wait_queue_head_t *gpio_wq;
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#endif
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#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
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static int virtual_gpio_ioctl(struct file *file, unsigned int cmd,
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unsigned long arg);
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#endif
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static int gpio_ioctl(struct inode *inode, struct file *file,
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unsigned int cmd, unsigned long arg);
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static ssize_t gpio_write(struct file *file, const char *buf, size_t count,
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loff_t *off);
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static int gpio_open(struct inode *inode, struct file *filp);
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static int gpio_release(struct inode *inode, struct file *filp);
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static unsigned int gpio_poll(struct file *filp,
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struct poll_table_struct *wait);
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/* private data per open() of this driver */
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struct gpio_private {
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struct gpio_private *next;
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/* The IO_CFG_WRITE_MODE_VALUE only support 8 bits: */
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unsigned char clk_mask;
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unsigned char data_mask;
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unsigned char write_msb;
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unsigned char pad1;
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/* These fields are generic */
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unsigned long highalarm, lowalarm;
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wait_queue_head_t alarm_wq;
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int minor;
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};
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/* linked list of alarms to check for */
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static struct gpio_private *alarmlist;
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static int gpio_some_alarms; /* Set if someone uses alarm */
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static unsigned long gpio_pa_high_alarms;
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static unsigned long gpio_pa_low_alarms;
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static DEFINE_SPINLOCK(alarm_lock);
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#define NUM_PORTS (GPIO_MINOR_LAST+1)
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#define GIO_REG_RD_ADDR(reg) \
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(volatile unsigned long *)(regi_gio + REG_RD_ADDR_gio_##reg)
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#define GIO_REG_WR_ADDR(reg) \
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(volatile unsigned long *)(regi_gio + REG_RD_ADDR_gio_##reg)
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unsigned long led_dummy;
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#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
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static unsigned long virtual_dummy;
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static unsigned long virtual_rw_pv_oe = CONFIG_ETRAX_DEF_GIO_PV_OE;
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static unsigned short cached_virtual_gpio_read;
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#endif
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static volatile unsigned long *data_out[NUM_PORTS] = {
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GIO_REG_WR_ADDR(rw_pa_dout),
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GIO_REG_WR_ADDR(rw_pb_dout),
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&led_dummy,
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GIO_REG_WR_ADDR(rw_pc_dout),
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GIO_REG_WR_ADDR(rw_pd_dout),
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GIO_REG_WR_ADDR(rw_pe_dout),
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#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
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&virtual_dummy,
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#endif
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};
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static volatile unsigned long *data_in[NUM_PORTS] = {
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GIO_REG_RD_ADDR(r_pa_din),
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GIO_REG_RD_ADDR(r_pb_din),
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&led_dummy,
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GIO_REG_RD_ADDR(r_pc_din),
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GIO_REG_RD_ADDR(r_pd_din),
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GIO_REG_RD_ADDR(r_pe_din),
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#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
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&virtual_dummy,
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#endif
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};
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static unsigned long changeable_dir[NUM_PORTS] = {
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CONFIG_ETRAX_PA_CHANGEABLE_DIR,
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CONFIG_ETRAX_PB_CHANGEABLE_DIR,
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0,
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CONFIG_ETRAX_PC_CHANGEABLE_DIR,
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CONFIG_ETRAX_PD_CHANGEABLE_DIR,
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CONFIG_ETRAX_PE_CHANGEABLE_DIR,
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#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
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CONFIG_ETRAX_PV_CHANGEABLE_DIR,
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#endif
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};
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static unsigned long changeable_bits[NUM_PORTS] = {
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CONFIG_ETRAX_PA_CHANGEABLE_BITS,
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CONFIG_ETRAX_PB_CHANGEABLE_BITS,
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0,
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CONFIG_ETRAX_PC_CHANGEABLE_BITS,
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CONFIG_ETRAX_PD_CHANGEABLE_BITS,
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CONFIG_ETRAX_PE_CHANGEABLE_BITS,
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#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
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CONFIG_ETRAX_PV_CHANGEABLE_BITS,
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#endif
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};
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static volatile unsigned long *dir_oe[NUM_PORTS] = {
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GIO_REG_WR_ADDR(rw_pa_oe),
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GIO_REG_WR_ADDR(rw_pb_oe),
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&led_dummy,
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GIO_REG_WR_ADDR(rw_pc_oe),
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GIO_REG_WR_ADDR(rw_pd_oe),
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GIO_REG_WR_ADDR(rw_pe_oe),
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#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
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&virtual_rw_pv_oe,
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#endif
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};
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static unsigned int gpio_poll(struct file *file, struct poll_table_struct *wait)
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{
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unsigned int mask = 0;
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struct gpio_private *priv = (struct gpio_private *)file->private_data;
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unsigned long data;
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poll_wait(file, &priv->alarm_wq, wait);
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if (priv->minor == GPIO_MINOR_A) {
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reg_gio_rw_intr_cfg intr_cfg;
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unsigned long tmp;
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unsigned long flags;
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local_irq_save(flags);
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data = REG_TYPE_CONV(unsigned long, reg_gio_r_pa_din,
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REG_RD(gio, regi_gio, r_pa_din));
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/* PA has support for interrupt
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* lets activate high for those low and with highalarm set
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*/
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intr_cfg = REG_RD(gio, regi_gio, rw_intr_cfg);
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tmp = ~data & priv->highalarm & 0xFF;
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if (tmp & (1 << 0))
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intr_cfg.pa0 = regk_gio_hi;
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if (tmp & (1 << 1))
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intr_cfg.pa1 = regk_gio_hi;
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if (tmp & (1 << 2))
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intr_cfg.pa2 = regk_gio_hi;
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if (tmp & (1 << 3))
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intr_cfg.pa3 = regk_gio_hi;
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if (tmp & (1 << 4))
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intr_cfg.pa4 = regk_gio_hi;
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if (tmp & (1 << 5))
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intr_cfg.pa5 = regk_gio_hi;
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if (tmp & (1 << 6))
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intr_cfg.pa6 = regk_gio_hi;
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if (tmp & (1 << 7))
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intr_cfg.pa7 = regk_gio_hi;
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/*
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* lets activate low for those high and with lowalarm set
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*/
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tmp = data & priv->lowalarm & 0xFF;
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if (tmp & (1 << 0))
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intr_cfg.pa0 = regk_gio_lo;
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if (tmp & (1 << 1))
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intr_cfg.pa1 = regk_gio_lo;
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if (tmp & (1 << 2))
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intr_cfg.pa2 = regk_gio_lo;
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if (tmp & (1 << 3))
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intr_cfg.pa3 = regk_gio_lo;
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if (tmp & (1 << 4))
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intr_cfg.pa4 = regk_gio_lo;
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if (tmp & (1 << 5))
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intr_cfg.pa5 = regk_gio_lo;
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if (tmp & (1 << 6))
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intr_cfg.pa6 = regk_gio_lo;
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if (tmp & (1 << 7))
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intr_cfg.pa7 = regk_gio_lo;
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REG_WR(gio, regi_gio, rw_intr_cfg, intr_cfg);
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local_irq_restore(flags);
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} else if (priv->minor <= GPIO_MINOR_E)
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data = *data_in[priv->minor];
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else
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return 0;
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if ((data & priv->highalarm) || (~data & priv->lowalarm))
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mask = POLLIN|POLLRDNORM;
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DP(printk(KERN_DEBUG "gpio_poll ready: mask 0x%08X\n", mask));
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return mask;
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}
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int etrax_gpio_wake_up_check(void)
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{
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struct gpio_private *priv;
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unsigned long data = 0;
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unsigned long flags;
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int ret = 0;
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spin_lock_irqsave(&alarm_lock, flags);
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priv = alarmlist;
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while (priv) {
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#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
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if (priv->minor == GPIO_MINOR_V)
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data = (unsigned long)cached_virtual_gpio_read;
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else {
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data = *data_in[priv->minor];
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if (priv->minor == GPIO_MINOR_A)
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priv->lowalarm |= (1 << CONFIG_ETRAX_VIRTUAL_GPIO_INTERRUPT_PA_PIN);
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}
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#else
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data = *data_in[priv->minor];
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#endif
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if ((data & priv->highalarm) ||
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(~data & priv->lowalarm)) {
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DP(printk(KERN_DEBUG
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"etrax_gpio_wake_up_check %i\n", priv->minor));
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wake_up_interruptible(&priv->alarm_wq);
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ret = 1;
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}
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priv = priv->next;
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}
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spin_unlock_irqrestore(&alarm_lock, flags);
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return ret;
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}
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static irqreturn_t
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gpio_poll_timer_interrupt(int irq, void *dev_id)
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{
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if (gpio_some_alarms)
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return IRQ_RETVAL(etrax_gpio_wake_up_check());
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return IRQ_NONE;
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}
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static irqreturn_t
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gpio_pa_interrupt(int irq, void *dev_id)
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{
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reg_gio_rw_intr_mask intr_mask;
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reg_gio_r_masked_intr masked_intr;
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reg_gio_rw_ack_intr ack_intr;
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unsigned long tmp;
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unsigned long tmp2;
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#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
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unsigned char enable_gpiov_ack = 0;
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#endif
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/* Find what PA interrupts are active */
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masked_intr = REG_RD(gio, regi_gio, r_masked_intr);
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tmp = REG_TYPE_CONV(unsigned long, reg_gio_r_masked_intr, masked_intr);
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/* Find those that we have enabled */
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spin_lock(&alarm_lock);
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tmp &= (gpio_pa_high_alarms | gpio_pa_low_alarms);
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spin_unlock(&alarm_lock);
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#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
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/* Something changed on virtual GPIO. Interrupt is acked by
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* reading the device.
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*/
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if (tmp & (1 << CONFIG_ETRAX_VIRTUAL_GPIO_INTERRUPT_PA_PIN)) {
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i2c_read(VIRT_I2C_ADDR, (void *)&cached_virtual_gpio_read,
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sizeof(cached_virtual_gpio_read));
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enable_gpiov_ack = 1;
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}
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#endif
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/* Ack them */
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ack_intr = REG_TYPE_CONV(reg_gio_rw_ack_intr, unsigned long, tmp);
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REG_WR(gio, regi_gio, rw_ack_intr, ack_intr);
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/* Disable those interrupts.. */
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intr_mask = REG_RD(gio, regi_gio, rw_intr_mask);
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tmp2 = REG_TYPE_CONV(unsigned long, reg_gio_rw_intr_mask, intr_mask);
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tmp2 &= ~tmp;
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#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
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/* Do not disable interrupt on virtual GPIO. Changes on virtual
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* pins are only noticed by an interrupt.
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*/
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if (enable_gpiov_ack)
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tmp2 |= (1 << CONFIG_ETRAX_VIRTUAL_GPIO_INTERRUPT_PA_PIN);
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#endif
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intr_mask = REG_TYPE_CONV(reg_gio_rw_intr_mask, unsigned long, tmp2);
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REG_WR(gio, regi_gio, rw_intr_mask, intr_mask);
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if (gpio_some_alarms)
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return IRQ_RETVAL(etrax_gpio_wake_up_check());
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return IRQ_NONE;
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}
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static ssize_t gpio_write(struct file *file, const char *buf, size_t count,
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loff_t *off)
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{
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struct gpio_private *priv = (struct gpio_private *)file->private_data;
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unsigned char data, clk_mask, data_mask, write_msb;
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unsigned long flags;
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unsigned long shadow;
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volatile unsigned long *port;
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ssize_t retval = count;
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/* Only bits 0-7 may be used for write operations but allow all
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devices except leds... */
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#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
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if (priv->minor == GPIO_MINOR_V)
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return -EFAULT;
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#endif
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if (priv->minor == GPIO_MINOR_LEDS)
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return -EFAULT;
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if (!access_ok(VERIFY_READ, buf, count))
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return -EFAULT;
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clk_mask = priv->clk_mask;
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data_mask = priv->data_mask;
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/* It must have been configured using the IO_CFG_WRITE_MODE */
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/* Perhaps a better error code? */
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if (clk_mask == 0 || data_mask == 0)
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return -EPERM;
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write_msb = priv->write_msb;
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D(printk(KERN_DEBUG "gpio_write: %lu to data 0x%02X clk 0x%02X "
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"msb: %i\n", count, data_mask, clk_mask, write_msb));
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port = data_out[priv->minor];
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while (count--) {
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int i;
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data = *buf++;
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if (priv->write_msb) {
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for (i = 7; i >= 0; i--) {
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local_irq_save(flags);
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shadow = *port;
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*port = shadow &= ~clk_mask;
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if (data & 1<<i)
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*port = shadow |= data_mask;
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else
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*port = shadow &= ~data_mask;
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/* For FPGA: min 5.0ns (DCC) before CCLK high */
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*port = shadow |= clk_mask;
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local_irq_restore(flags);
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}
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} else {
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for (i = 0; i <= 7; i++) {
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local_irq_save(flags);
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shadow = *port;
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*port = shadow &= ~clk_mask;
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if (data & 1<<i)
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*port = shadow |= data_mask;
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else
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*port = shadow &= ~data_mask;
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/* For FPGA: min 5.0ns (DCC) before CCLK high */
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*port = shadow |= clk_mask;
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local_irq_restore(flags);
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}
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}
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}
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return retval;
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}
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static int
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gpio_open(struct inode *inode, struct file *filp)
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{
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struct gpio_private *priv;
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int p = iminor(inode);
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if (p > GPIO_MINOR_LAST)
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return -EINVAL;
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priv = kmalloc(sizeof(struct gpio_private), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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lock_kernel();
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memset(priv, 0, sizeof(*priv));
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priv->minor = p;
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/* initialize the io/alarm struct */
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priv->clk_mask = 0;
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priv->data_mask = 0;
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priv->highalarm = 0;
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priv->lowalarm = 0;
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init_waitqueue_head(&priv->alarm_wq);
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filp->private_data = (void *)priv;
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/* link it into our alarmlist */
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spin_lock_irq(&alarm_lock);
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priv->next = alarmlist;
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alarmlist = priv;
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spin_unlock_irq(&alarm_lock);
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unlock_kernel();
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return 0;
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}
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static int
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gpio_release(struct inode *inode, struct file *filp)
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{
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struct gpio_private *p;
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struct gpio_private *todel;
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/* local copies while updating them: */
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unsigned long a_high, a_low;
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unsigned long some_alarms;
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/* unlink from alarmlist and free the private structure */
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spin_lock_irq(&alarm_lock);
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p = alarmlist;
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todel = (struct gpio_private *)filp->private_data;
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if (p == todel) {
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alarmlist = todel->next;
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} else {
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while (p->next != todel)
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p = p->next;
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p->next = todel->next;
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}
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kfree(todel);
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/* Check if there are still any alarms set */
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p = alarmlist;
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some_alarms = 0;
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a_high = 0;
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a_low = 0;
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while (p) {
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if (p->minor == GPIO_MINOR_A) {
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#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
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p->lowalarm |= (1 << CONFIG_ETRAX_VIRTUAL_GPIO_INTERRUPT_PA_PIN);
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#endif
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a_high |= p->highalarm;
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a_low |= p->lowalarm;
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}
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|
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if (p->highalarm | p->lowalarm)
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some_alarms = 1;
|
|
p = p->next;
|
|
}
|
|
|
|
#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
|
|
/* Variables 'some_alarms' and 'a_low' needs to be set here again
|
|
* to ensure that interrupt for virtual GPIO is handled.
|
|
*/
|
|
some_alarms = 1;
|
|
a_low |= (1 << CONFIG_ETRAX_VIRTUAL_GPIO_INTERRUPT_PA_PIN);
|
|
#endif
|
|
|
|
gpio_some_alarms = some_alarms;
|
|
gpio_pa_high_alarms = a_high;
|
|
gpio_pa_low_alarms = a_low;
|
|
spin_unlock_irq(&alarm_lock);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/* Main device API. ioctl's to read/set/clear bits, as well as to
|
|
* set alarms to wait for using a subsequent select().
|
|
*/
|
|
|
|
inline unsigned long setget_input(struct gpio_private *priv, unsigned long arg)
|
|
{
|
|
/* Set direction 0=unchanged 1=input,
|
|
* return mask with 1=input
|
|
*/
|
|
unsigned long flags;
|
|
unsigned long dir_shadow;
|
|
|
|
local_irq_save(flags);
|
|
dir_shadow = *dir_oe[priv->minor];
|
|
dir_shadow &= ~(arg & changeable_dir[priv->minor]);
|
|
*dir_oe[priv->minor] = dir_shadow;
|
|
local_irq_restore(flags);
|
|
|
|
if (priv->minor == GPIO_MINOR_A)
|
|
dir_shadow ^= 0xFF; /* Only 8 bits */
|
|
#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
|
|
else if (priv->minor == GPIO_MINOR_V)
|
|
dir_shadow ^= 0xFFFF; /* Only 16 bits */
|
|
#endif
|
|
else
|
|
dir_shadow ^= 0x3FFFF; /* Only 18 bits */
|
|
return dir_shadow;
|
|
|
|
} /* setget_input */
|
|
|
|
inline unsigned long setget_output(struct gpio_private *priv, unsigned long arg)
|
|
{
|
|
unsigned long flags;
|
|
unsigned long dir_shadow;
|
|
|
|
local_irq_save(flags);
|
|
dir_shadow = *dir_oe[priv->minor];
|
|
dir_shadow |= (arg & changeable_dir[priv->minor]);
|
|
*dir_oe[priv->minor] = dir_shadow;
|
|
local_irq_restore(flags);
|
|
return dir_shadow;
|
|
} /* setget_output */
|
|
|
|
static int
|
|
gpio_leds_ioctl(unsigned int cmd, unsigned long arg);
|
|
|
|
static int
|
|
gpio_ioctl(struct inode *inode, struct file *file,
|
|
unsigned int cmd, unsigned long arg)
|
|
{
|
|
unsigned long flags;
|
|
unsigned long val;
|
|
unsigned long shadow;
|
|
struct gpio_private *priv = (struct gpio_private *)file->private_data;
|
|
if (_IOC_TYPE(cmd) != ETRAXGPIO_IOCTYPE)
|
|
return -EINVAL;
|
|
|
|
#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
|
|
if (priv->minor == GPIO_MINOR_V)
|
|
return virtual_gpio_ioctl(file, cmd, arg);
|
|
#endif
|
|
|
|
switch (_IOC_NR(cmd)) {
|
|
case IO_READBITS: /* Use IO_READ_INBITS and IO_READ_OUTBITS instead */
|
|
/* Read the port. */
|
|
return *data_in[priv->minor];
|
|
break;
|
|
case IO_SETBITS:
|
|
local_irq_save(flags);
|
|
/* Set changeable bits with a 1 in arg. */
|
|
shadow = *data_out[priv->minor];
|
|
shadow |= (arg & changeable_bits[priv->minor]);
|
|
*data_out[priv->minor] = shadow;
|
|
local_irq_restore(flags);
|
|
break;
|
|
case IO_CLRBITS:
|
|
local_irq_save(flags);
|
|
/* Clear changeable bits with a 1 in arg. */
|
|
shadow = *data_out[priv->minor];
|
|
shadow &= ~(arg & changeable_bits[priv->minor]);
|
|
*data_out[priv->minor] = shadow;
|
|
local_irq_restore(flags);
|
|
break;
|
|
case IO_HIGHALARM:
|
|
/* Set alarm when bits with 1 in arg go high. */
|
|
priv->highalarm |= arg;
|
|
spin_lock_irqsave(&alarm_lock, flags);
|
|
gpio_some_alarms = 1;
|
|
if (priv->minor == GPIO_MINOR_A)
|
|
gpio_pa_high_alarms |= arg;
|
|
spin_unlock_irqrestore(&alarm_lock, flags);
|
|
break;
|
|
case IO_LOWALARM:
|
|
/* Set alarm when bits with 1 in arg go low. */
|
|
priv->lowalarm |= arg;
|
|
spin_lock_irqsave(&alarm_lock, flags);
|
|
gpio_some_alarms = 1;
|
|
if (priv->minor == GPIO_MINOR_A)
|
|
gpio_pa_low_alarms |= arg;
|
|
spin_unlock_irqrestore(&alarm_lock, flags);
|
|
break;
|
|
case IO_CLRALARM:
|
|
/* Clear alarm for bits with 1 in arg. */
|
|
priv->highalarm &= ~arg;
|
|
priv->lowalarm &= ~arg;
|
|
spin_lock_irqsave(&alarm_lock, flags);
|
|
if (priv->minor == GPIO_MINOR_A) {
|
|
if (gpio_pa_high_alarms & arg ||
|
|
gpio_pa_low_alarms & arg)
|
|
/* Must update the gpio_pa_*alarms masks */
|
|
;
|
|
}
|
|
spin_unlock_irqrestore(&alarm_lock, flags);
|
|
break;
|
|
case IO_READDIR: /* Use IO_SETGET_INPUT/OUTPUT instead! */
|
|
/* Read direction 0=input 1=output */
|
|
return *dir_oe[priv->minor];
|
|
case IO_SETINPUT: /* Use IO_SETGET_INPUT instead! */
|
|
/* Set direction 0=unchanged 1=input,
|
|
* return mask with 1=input
|
|
*/
|
|
return setget_input(priv, arg);
|
|
break;
|
|
case IO_SETOUTPUT: /* Use IO_SETGET_OUTPUT instead! */
|
|
/* Set direction 0=unchanged 1=output,
|
|
* return mask with 1=output
|
|
*/
|
|
return setget_output(priv, arg);
|
|
|
|
case IO_CFG_WRITE_MODE:
|
|
{
|
|
unsigned long dir_shadow;
|
|
dir_shadow = *dir_oe[priv->minor];
|
|
|
|
priv->clk_mask = arg & 0xFF;
|
|
priv->data_mask = (arg >> 8) & 0xFF;
|
|
priv->write_msb = (arg >> 16) & 0x01;
|
|
/* Check if we're allowed to change the bits and
|
|
* the direction is correct
|
|
*/
|
|
if (!((priv->clk_mask & changeable_bits[priv->minor]) &&
|
|
(priv->data_mask & changeable_bits[priv->minor]) &&
|
|
(priv->clk_mask & dir_shadow) &&
|
|
(priv->data_mask & dir_shadow))) {
|
|
priv->clk_mask = 0;
|
|
priv->data_mask = 0;
|
|
return -EPERM;
|
|
}
|
|
break;
|
|
}
|
|
case IO_READ_INBITS:
|
|
/* *arg is result of reading the input pins */
|
|
val = *data_in[priv->minor];
|
|
if (copy_to_user((unsigned long *)arg, &val, sizeof(val)))
|
|
return -EFAULT;
|
|
return 0;
|
|
break;
|
|
case IO_READ_OUTBITS:
|
|
/* *arg is result of reading the output shadow */
|
|
val = *data_out[priv->minor];
|
|
if (copy_to_user((unsigned long *)arg, &val, sizeof(val)))
|
|
return -EFAULT;
|
|
break;
|
|
case IO_SETGET_INPUT:
|
|
/* bits set in *arg is set to input,
|
|
* *arg updated with current input pins.
|
|
*/
|
|
if (copy_from_user(&val, (unsigned long *)arg, sizeof(val)))
|
|
return -EFAULT;
|
|
val = setget_input(priv, val);
|
|
if (copy_to_user((unsigned long *)arg, &val, sizeof(val)))
|
|
return -EFAULT;
|
|
break;
|
|
case IO_SETGET_OUTPUT:
|
|
/* bits set in *arg is set to output,
|
|
* *arg updated with current output pins.
|
|
*/
|
|
if (copy_from_user(&val, (unsigned long *)arg, sizeof(val)))
|
|
return -EFAULT;
|
|
val = setget_output(priv, val);
|
|
if (copy_to_user((unsigned long *)arg, &val, sizeof(val)))
|
|
return -EFAULT;
|
|
break;
|
|
default:
|
|
if (priv->minor == GPIO_MINOR_LEDS)
|
|
return gpio_leds_ioctl(cmd, arg);
|
|
else
|
|
return -EINVAL;
|
|
} /* switch */
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
|
|
static int
|
|
virtual_gpio_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
|
|
{
|
|
unsigned long flags;
|
|
unsigned short val;
|
|
unsigned short shadow;
|
|
struct gpio_private *priv = (struct gpio_private *)file->private_data;
|
|
|
|
switch (_IOC_NR(cmd)) {
|
|
case IO_SETBITS:
|
|
local_irq_save(flags);
|
|
/* Set changeable bits with a 1 in arg. */
|
|
i2c_read(VIRT_I2C_ADDR, (void *)&shadow, sizeof(shadow));
|
|
shadow |= ~*dir_oe[priv->minor];
|
|
shadow |= (arg & changeable_bits[priv->minor]);
|
|
i2c_write(VIRT_I2C_ADDR, (void *)&shadow, sizeof(shadow));
|
|
local_irq_restore(flags);
|
|
break;
|
|
case IO_CLRBITS:
|
|
local_irq_save(flags);
|
|
/* Clear changeable bits with a 1 in arg. */
|
|
i2c_read(VIRT_I2C_ADDR, (void *)&shadow, sizeof(shadow));
|
|
shadow |= ~*dir_oe[priv->minor];
|
|
shadow &= ~(arg & changeable_bits[priv->minor]);
|
|
i2c_write(VIRT_I2C_ADDR, (void *)&shadow, sizeof(shadow));
|
|
local_irq_restore(flags);
|
|
break;
|
|
case IO_HIGHALARM:
|
|
/* Set alarm when bits with 1 in arg go high. */
|
|
priv->highalarm |= arg;
|
|
spin_lock(&alarm_lock);
|
|
gpio_some_alarms = 1;
|
|
spin_unlock(&alarm_lock);
|
|
break;
|
|
case IO_LOWALARM:
|
|
/* Set alarm when bits with 1 in arg go low. */
|
|
priv->lowalarm |= arg;
|
|
spin_lock(&alarm_lock);
|
|
gpio_some_alarms = 1;
|
|
spin_unlock(&alarm_lock);
|
|
break;
|
|
case IO_CLRALARM:
|
|
/* Clear alarm for bits with 1 in arg. */
|
|
priv->highalarm &= ~arg;
|
|
priv->lowalarm &= ~arg;
|
|
spin_lock(&alarm_lock);
|
|
spin_unlock(&alarm_lock);
|
|
break;
|
|
case IO_CFG_WRITE_MODE:
|
|
{
|
|
unsigned long dir_shadow;
|
|
dir_shadow = *dir_oe[priv->minor];
|
|
|
|
priv->clk_mask = arg & 0xFF;
|
|
priv->data_mask = (arg >> 8) & 0xFF;
|
|
priv->write_msb = (arg >> 16) & 0x01;
|
|
/* Check if we're allowed to change the bits and
|
|
* the direction is correct
|
|
*/
|
|
if (!((priv->clk_mask & changeable_bits[priv->minor]) &&
|
|
(priv->data_mask & changeable_bits[priv->minor]) &&
|
|
(priv->clk_mask & dir_shadow) &&
|
|
(priv->data_mask & dir_shadow))) {
|
|
priv->clk_mask = 0;
|
|
priv->data_mask = 0;
|
|
return -EPERM;
|
|
}
|
|
break;
|
|
}
|
|
case IO_READ_INBITS:
|
|
/* *arg is result of reading the input pins */
|
|
val = cached_virtual_gpio_read;
|
|
val &= ~*dir_oe[priv->minor];
|
|
if (copy_to_user((unsigned long *)arg, &val, sizeof(val)))
|
|
return -EFAULT;
|
|
return 0;
|
|
break;
|
|
case IO_READ_OUTBITS:
|
|
/* *arg is result of reading the output shadow */
|
|
i2c_read(VIRT_I2C_ADDR, (void *)&val, sizeof(val));
|
|
val &= *dir_oe[priv->minor];
|
|
if (copy_to_user((unsigned long *)arg, &val, sizeof(val)))
|
|
return -EFAULT;
|
|
break;
|
|
case IO_SETGET_INPUT:
|
|
{
|
|
/* bits set in *arg is set to input,
|
|
* *arg updated with current input pins.
|
|
*/
|
|
unsigned short input_mask = ~*dir_oe[priv->minor];
|
|
if (copy_from_user(&val, (unsigned long *)arg, sizeof(val)))
|
|
return -EFAULT;
|
|
val = setget_input(priv, val);
|
|
if (copy_to_user((unsigned long *)arg, &val, sizeof(val)))
|
|
return -EFAULT;
|
|
if ((input_mask & val) != input_mask) {
|
|
/* Input pins changed. All ports desired as input
|
|
* should be set to logic 1.
|
|
*/
|
|
unsigned short change = input_mask ^ val;
|
|
i2c_read(VIRT_I2C_ADDR, (void *)&shadow,
|
|
sizeof(shadow));
|
|
shadow &= ~change;
|
|
shadow |= val;
|
|
i2c_write(VIRT_I2C_ADDR, (void *)&shadow,
|
|
sizeof(shadow));
|
|
}
|
|
break;
|
|
}
|
|
case IO_SETGET_OUTPUT:
|
|
/* bits set in *arg is set to output,
|
|
* *arg updated with current output pins.
|
|
*/
|
|
if (copy_from_user(&val, (unsigned long *)arg, sizeof(val)))
|
|
return -EFAULT;
|
|
val = setget_output(priv, val);
|
|
if (copy_to_user((unsigned long *)arg, &val, sizeof(val)))
|
|
return -EFAULT;
|
|
break;
|
|
default:
|
|
return -EINVAL;
|
|
} /* switch */
|
|
return 0;
|
|
}
|
|
#endif /* CONFIG_ETRAX_VIRTUAL_GPIO */
|
|
|
|
static int
|
|
gpio_leds_ioctl(unsigned int cmd, unsigned long arg)
|
|
{
|
|
unsigned char green;
|
|
unsigned char red;
|
|
|
|
switch (_IOC_NR(cmd)) {
|
|
case IO_LEDACTIVE_SET:
|
|
green = ((unsigned char) arg) & 1;
|
|
red = (((unsigned char) arg) >> 1) & 1;
|
|
CRIS_LED_ACTIVE_SET_G(green);
|
|
CRIS_LED_ACTIVE_SET_R(red);
|
|
break;
|
|
|
|
default:
|
|
return -EINVAL;
|
|
} /* switch */
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct file_operations gpio_fops = {
|
|
.owner = THIS_MODULE,
|
|
.poll = gpio_poll,
|
|
.ioctl = gpio_ioctl,
|
|
.write = gpio_write,
|
|
.open = gpio_open,
|
|
.release = gpio_release,
|
|
};
|
|
|
|
#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
|
|
static void
|
|
virtual_gpio_init(void)
|
|
{
|
|
reg_gio_rw_intr_cfg intr_cfg;
|
|
reg_gio_rw_intr_mask intr_mask;
|
|
unsigned short shadow;
|
|
|
|
shadow = ~virtual_rw_pv_oe; /* Input ports should be set to logic 1 */
|
|
shadow |= CONFIG_ETRAX_DEF_GIO_PV_OUT;
|
|
i2c_write(VIRT_I2C_ADDR, (void *)&shadow, sizeof(shadow));
|
|
|
|
/* Set interrupt mask and on what state the interrupt shall trigger.
|
|
* For virtual gpio the interrupt shall trigger on logic '0'.
|
|
*/
|
|
intr_cfg = REG_RD(gio, regi_gio, rw_intr_cfg);
|
|
intr_mask = REG_RD(gio, regi_gio, rw_intr_mask);
|
|
|
|
switch (CONFIG_ETRAX_VIRTUAL_GPIO_INTERRUPT_PA_PIN) {
|
|
case 0:
|
|
intr_cfg.pa0 = regk_gio_lo;
|
|
intr_mask.pa0 = regk_gio_yes;
|
|
break;
|
|
case 1:
|
|
intr_cfg.pa1 = regk_gio_lo;
|
|
intr_mask.pa1 = regk_gio_yes;
|
|
break;
|
|
case 2:
|
|
intr_cfg.pa2 = regk_gio_lo;
|
|
intr_mask.pa2 = regk_gio_yes;
|
|
break;
|
|
case 3:
|
|
intr_cfg.pa3 = regk_gio_lo;
|
|
intr_mask.pa3 = regk_gio_yes;
|
|
break;
|
|
case 4:
|
|
intr_cfg.pa4 = regk_gio_lo;
|
|
intr_mask.pa4 = regk_gio_yes;
|
|
break;
|
|
case 5:
|
|
intr_cfg.pa5 = regk_gio_lo;
|
|
intr_mask.pa5 = regk_gio_yes;
|
|
break;
|
|
case 6:
|
|
intr_cfg.pa6 = regk_gio_lo;
|
|
intr_mask.pa6 = regk_gio_yes;
|
|
break;
|
|
case 7:
|
|
intr_cfg.pa7 = regk_gio_lo;
|
|
intr_mask.pa7 = regk_gio_yes;
|
|
break;
|
|
}
|
|
|
|
REG_WR(gio, regi_gio, rw_intr_cfg, intr_cfg);
|
|
REG_WR(gio, regi_gio, rw_intr_mask, intr_mask);
|
|
|
|
gpio_pa_low_alarms |= (1 << CONFIG_ETRAX_VIRTUAL_GPIO_INTERRUPT_PA_PIN);
|
|
gpio_some_alarms = 1;
|
|
}
|
|
#endif
|
|
|
|
/* main driver initialization routine, called from mem.c */
|
|
|
|
static __init int
|
|
gpio_init(void)
|
|
{
|
|
int res;
|
|
|
|
/* do the formalities */
|
|
|
|
res = register_chrdev(GPIO_MAJOR, gpio_name, &gpio_fops);
|
|
if (res < 0) {
|
|
printk(KERN_ERR "gpio: couldn't get a major number.\n");
|
|
return res;
|
|
}
|
|
|
|
/* Clear all leds */
|
|
CRIS_LED_NETWORK_GRP0_SET(0);
|
|
CRIS_LED_NETWORK_GRP1_SET(0);
|
|
CRIS_LED_ACTIVE_SET(0);
|
|
CRIS_LED_DISK_READ(0);
|
|
CRIS_LED_DISK_WRITE(0);
|
|
|
|
printk(KERN_INFO "ETRAX FS GPIO driver v2.5, (c) 2003-2007 "
|
|
"Axis Communications AB\n");
|
|
/* We call etrax_gpio_wake_up_check() from timer interrupt and
|
|
* from cpu_idle() in kernel/process.c
|
|
* The check in cpu_idle() reduces latency from ~15 ms to ~6 ms
|
|
* in some tests.
|
|
*/
|
|
if (request_irq(TIMER0_INTR_VECT, gpio_poll_timer_interrupt,
|
|
IRQF_SHARED | IRQF_DISABLED, "gpio poll", &alarmlist))
|
|
printk(KERN_ERR "timer0 irq for gpio\n");
|
|
|
|
if (request_irq(GIO_INTR_VECT, gpio_pa_interrupt,
|
|
IRQF_SHARED | IRQF_DISABLED, "gpio PA", &alarmlist))
|
|
printk(KERN_ERR "PA irq for gpio\n");
|
|
|
|
#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
|
|
virtual_gpio_init();
|
|
#endif
|
|
|
|
return res;
|
|
}
|
|
|
|
/* this makes sure that gpio_init is called during kernel boot */
|
|
|
|
module_init(gpio_init);
|