187 lines
5.1 KiB
C
187 lines
5.1 KiB
C
/*
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* Copyright (C) 1997,1998 Russell King
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* Copyright (C) 1999 ARM Limited
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* Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
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* Copyright (c) 2008 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ASM_ARCH_MXC_MX1_H__
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#define __ASM_ARCH_MXC_MX1_H__
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#ifndef __ASM_ARCH_MXC_HARDWARE_H__
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#error "Do not include directly."
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#endif
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#include <mach/vmalloc.h>
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/*
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* Memory map
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*/
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#define IMX_IO_PHYS 0x00200000
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#define IMX_IO_SIZE 0x00100000
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#define IMX_IO_BASE VMALLOC_END
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#define IMX_CS0_PHYS 0x10000000
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#define IMX_CS0_SIZE 0x02000000
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#define IMX_CS1_PHYS 0x12000000
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#define IMX_CS1_SIZE 0x01000000
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#define IMX_CS2_PHYS 0x13000000
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#define IMX_CS2_SIZE 0x01000000
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#define IMX_CS3_PHYS 0x14000000
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#define IMX_CS3_SIZE 0x01000000
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#define IMX_CS4_PHYS 0x15000000
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#define IMX_CS4_SIZE 0x01000000
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#define IMX_CS5_PHYS 0x16000000
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#define IMX_CS5_SIZE 0x01000000
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/*
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* Register BASEs, based on OFFSETs
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*/
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#define AIPI1_BASE_ADDR (0x00000 + IMX_IO_PHYS)
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#define WDT_BASE_ADDR (0x01000 + IMX_IO_PHYS)
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#define TIM1_BASE_ADDR (0x02000 + IMX_IO_PHYS)
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#define TIM2_BASE_ADDR (0x03000 + IMX_IO_PHYS)
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#define RTC_BASE_ADDR (0x04000 + IMX_IO_PHYS)
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#define LCDC_BASE_ADDR (0x05000 + IMX_IO_PHYS)
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#define UART1_BASE_ADDR (0x06000 + IMX_IO_PHYS)
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#define UART2_BASE_ADDR (0x07000 + IMX_IO_PHYS)
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#define PWM_BASE_ADDR (0x08000 + IMX_IO_PHYS)
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#define DMA_BASE_ADDR (0x09000 + IMX_IO_PHYS)
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#define AIPI2_BASE_ADDR (0x10000 + IMX_IO_PHYS)
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#define SIM_BASE_ADDR (0x11000 + IMX_IO_PHYS)
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#define USBD_BASE_ADDR (0x12000 + IMX_IO_PHYS)
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#define SPI1_BASE_ADDR (0x13000 + IMX_IO_PHYS)
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#define MMC_BASE_ADDR (0x14000 + IMX_IO_PHYS)
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#define ASP_BASE_ADDR (0x15000 + IMX_IO_PHYS)
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#define BTA_BASE_ADDR (0x16000 + IMX_IO_PHYS)
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#define I2C_BASE_ADDR (0x17000 + IMX_IO_PHYS)
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#define SSI_BASE_ADDR (0x18000 + IMX_IO_PHYS)
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#define SPI2_BASE_ADDR (0x19000 + IMX_IO_PHYS)
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#define MSHC_BASE_ADDR (0x1A000 + IMX_IO_PHYS)
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#define CCM_BASE_ADDR (0x1B000 + IMX_IO_PHYS)
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#define SCM_BASE_ADDR (0x1B804 + IMX_IO_PHYS)
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#define GPIO_BASE_ADDR (0x1C000 + IMX_IO_PHYS)
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#define EIM_BASE_ADDR (0x20000 + IMX_IO_PHYS)
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#define SDRAMC_BASE_ADDR (0x21000 + IMX_IO_PHYS)
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#define MMA_BASE_ADDR (0x22000 + IMX_IO_PHYS)
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#define AVIC_BASE_ADDR (0x23000 + IMX_IO_PHYS)
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#define CSI_BASE_ADDR (0x24000 + IMX_IO_PHYS)
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/* macro to get at IO space when running virtually */
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#define IO_ADDRESS(x) ((x) - IMX_IO_PHYS + IMX_IO_BASE)
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/* define macros needed for entry-macro.S */
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#define AVIC_IO_ADDRESS(x) IO_ADDRESS(x)
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/* fixed interrput numbers */
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#define INT_SOFTINT 0
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#define CSI_INT 6
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#define DSPA_MAC_INT 7
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#define DSPA_INT 8
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#define COMP_INT 9
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#define MSHC_XINT 10
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#define GPIO_INT_PORTA 11
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#define GPIO_INT_PORTB 12
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#define GPIO_INT_PORTC 13
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#define LCDC_INT 14
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#define SIM_INT 15
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#define SIM_DATA_INT 16
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#define RTC_INT 17
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#define RTC_SAMINT 18
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#define UART2_MINT_PFERR 19
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#define UART2_MINT_RTS 20
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#define UART2_MINT_DTR 21
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#define UART2_MINT_UARTC 22
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#define UART2_MINT_TX 23
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#define UART2_MINT_RX 24
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#define UART1_MINT_PFERR 25
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#define UART1_MINT_RTS 26
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#define UART1_MINT_DTR 27
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#define UART1_MINT_UARTC 28
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#define UART1_MINT_TX 29
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#define UART1_MINT_RX 30
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#define VOICE_DAC_INT 31
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#define VOICE_ADC_INT 32
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#define PEN_DATA_INT 33
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#define PWM_INT 34
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#define SDHC_INT 35
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#define I2C_INT 39
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#define CSPI_INT 41
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#define SSI_TX_INT 42
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#define SSI_TX_ERR_INT 43
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#define SSI_RX_INT 44
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#define SSI_RX_ERR_INT 45
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#define TOUCH_INT 46
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#define USBD_INT0 47
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#define USBD_INT1 48
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#define USBD_INT2 49
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#define USBD_INT3 50
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#define USBD_INT4 51
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#define USBD_INT5 52
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#define USBD_INT6 53
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#define BTSYS_INT 55
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#define BTTIM_INT 56
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#define BTWUI_INT 57
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#define TIM2_INT 58
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#define TIM1_INT 59
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#define DMA_ERR 60
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#define DMA_INT 61
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#define GPIO_INT_PORTD 62
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#define WDT_INT 63
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/* gpio and gpio based interrupt handling */
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#define GPIO_DR 0x1C
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#define GPIO_GDIR 0x00
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#define GPIO_PSR 0x24
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#define GPIO_ICR1 0x28
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#define GPIO_ICR2 0x2C
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#define GPIO_IMR 0x30
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#define GPIO_ISR 0x34
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#define GPIO_INT_LOW_LEV 0x3
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#define GPIO_INT_HIGH_LEV 0x2
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#define GPIO_INT_RISE_EDGE 0x0
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#define GPIO_INT_FALL_EDGE 0x1
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#define GPIO_INT_NONE 0x4
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/* DMA */
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#define DMA_REQ_UART3_T 2
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#define DMA_REQ_UART3_R 3
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#define DMA_REQ_SSI2_T 4
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#define DMA_REQ_SSI2_R 5
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#define DMA_REQ_CSI_STAT 6
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#define DMA_REQ_CSI_R 7
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#define DMA_REQ_MSHC 8
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#define DMA_REQ_DSPA_DCT_DOUT 9
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#define DMA_REQ_DSPA_DCT_DIN 10
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#define DMA_REQ_DSPA_MAC 11
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#define DMA_REQ_EXT 12
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#define DMA_REQ_SDHC 13
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#define DMA_REQ_SPI1_R 14
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#define DMA_REQ_SPI1_T 15
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#define DMA_REQ_SSI_T 16
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#define DMA_REQ_SSI_R 17
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#define DMA_REQ_ASP_DAC 18
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#define DMA_REQ_ASP_ADC 19
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#define DMA_REQ_USP_EP(x) (20 + (x))
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#define DMA_REQ_SPI2_R 26
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#define DMA_REQ_SPI2_T 27
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#define DMA_REQ_UART2_T 28
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#define DMA_REQ_UART2_R 29
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#define DMA_REQ_UART1_T 30
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#define DMA_REQ_UART1_R 31
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/* mandatory for CONFIG_DEBUG_LL */
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#define MXC_LL_UART_PADDR UART1_BASE_ADDR
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#define MXC_LL_UART_VADDR IO_ADDRESS(UART1_BASE_ADDR)
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#endif /* __ASM_ARCH_MXC_MX1_H__ */
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