46 lines
1.4 KiB
C
46 lines
1.4 KiB
C
/*
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* IRAM
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*/
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#define MX31_IRAM_BASE_ADDR 0x1FFC0000 /* internal ram */
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#define MX31_IRAM_SIZE SZ_16K
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#define OTG_BASE_ADDR (AIPS1_BASE_ADDR + 0x00088000)
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#define ATA_BASE_ADDR (AIPS1_BASE_ADDR + 0x0008C000)
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#define UART4_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B0000)
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#define UART5_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B4000)
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#define MMC_SDHC1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00004000)
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#define MMC_SDHC2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00008000)
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#define SIM1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00018000)
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#define IIM_BASE_ADDR (SPBA0_BASE_ADDR + 0x0001C000)
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#define CSPI3_BASE_ADDR (AIPS2_BASE_ADDR + 0x00084000)
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#define FIRI_BASE_ADDR (AIPS2_BASE_ADDR + 0x0008C000)
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#define SCM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000AE000)
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#define SMN_BASE_ADDR (AIPS2_BASE_ADDR + 0x000AF000)
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#define MPEG4_ENC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C8000)
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#define MX31_NFC_BASE_ADDR (X_MEMC_BASE_ADDR + 0x0000)
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#define MXC_INT_MPEG4_ENCODER 5
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#define MXC_INT_FIRI 7
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#define MX31_INT_MMC_SDHC2 8
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#define MXC_INT_MMC_SDHC1 9
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#define MX31_INT_SSI2 11
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#define MX31_INT_SSI1 12
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#define MXC_INT_MBX 16
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#define MXC_INT_CSPI3 17
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#define MXC_INT_SIM2 20
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#define MXC_INT_SIM1 21
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#define MXC_INT_CCM_DVFS 31
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#define MXC_INT_USB1 35
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#define MXC_INT_USB2 36
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#define MXC_INT_USB3 37
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#define MXC_INT_USB4 38
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#define MXC_INT_MSHC2 40
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#define MXC_INT_UART4 46
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#define MXC_INT_UART5 47
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#define MXC_INT_CCM 53
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#define MXC_INT_PCMCIA 54
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