898 lines
24 KiB
C
898 lines
24 KiB
C
/*
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* Architecture-specific setup.
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*
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* Copyright (C) 1998-2001, 2003-2004 Hewlett-Packard Co
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* David Mosberger-Tang <davidm@hpl.hp.com>
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* Stephane Eranian <eranian@hpl.hp.com>
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* Copyright (C) 2000, 2004 Intel Corp
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* Rohit Seth <rohit.seth@intel.com>
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* Suresh Siddha <suresh.b.siddha@intel.com>
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* Gordon Jin <gordon.jin@intel.com>
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* Copyright (C) 1999 VA Linux Systems
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* Copyright (C) 1999 Walt Drummond <drummond@valinux.com>
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*
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* 12/26/04 S.Siddha, G.Jin, R.Seth
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* Add multi-threading and multi-core detection
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* 11/12/01 D.Mosberger Convert get_cpuinfo() to seq_file based show_cpuinfo().
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* 04/04/00 D.Mosberger renamed cpu_initialized to cpu_online_map
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* 03/31/00 R.Seth cpu_initialized and current->processor fixes
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* 02/04/00 D.Mosberger some more get_cpuinfo fixes...
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* 02/01/00 R.Seth fixed get_cpuinfo for SMP
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* 01/07/99 S.Eranian added the support for command line argument
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* 06/24/99 W.Drummond added boot_cpu_data.
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* 05/28/05 Z. Menyhart Dynamic stride size for "flush_icache_range()"
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*/
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/acpi.h>
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#include <linux/bootmem.h>
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#include <linux/console.h>
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#include <linux/delay.h>
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#include <linux/kernel.h>
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#include <linux/reboot.h>
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#include <linux/sched.h>
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#include <linux/seq_file.h>
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#include <linux/string.h>
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#include <linux/threads.h>
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#include <linux/screen_info.h>
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#include <linux/dmi.h>
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#include <linux/serial.h>
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#include <linux/serial_core.h>
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#include <linux/efi.h>
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#include <linux/initrd.h>
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#include <linux/pm.h>
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#include <linux/cpufreq.h>
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#include <asm/ia32.h>
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#include <asm/machvec.h>
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#include <asm/mca.h>
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#include <asm/meminit.h>
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#include <asm/page.h>
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#include <asm/patch.h>
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#include <asm/pgtable.h>
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#include <asm/processor.h>
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#include <asm/sal.h>
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#include <asm/sections.h>
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#include <asm/serial.h>
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#include <asm/setup.h>
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#include <asm/smp.h>
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#include <asm/system.h>
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#include <asm/unistd.h>
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#include <asm/system.h>
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#if defined(CONFIG_SMP) && (IA64_CPU_SIZE > PAGE_SIZE)
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# error "struct cpuinfo_ia64 too big!"
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#endif
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#ifdef CONFIG_SMP
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unsigned long __per_cpu_offset[NR_CPUS];
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EXPORT_SYMBOL(__per_cpu_offset);
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#endif
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extern void ia64_setup_printk_clock(void);
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DEFINE_PER_CPU(struct cpuinfo_ia64, cpu_info);
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DEFINE_PER_CPU(unsigned long, local_per_cpu_offset);
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DEFINE_PER_CPU(unsigned long, ia64_phys_stacked_size_p8);
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unsigned long ia64_cycles_per_usec;
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struct ia64_boot_param *ia64_boot_param;
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struct screen_info screen_info;
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unsigned long vga_console_iobase;
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unsigned long vga_console_membase;
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static struct resource data_resource = {
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.name = "Kernel data",
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.flags = IORESOURCE_BUSY | IORESOURCE_MEM
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};
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static struct resource code_resource = {
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.name = "Kernel code",
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.flags = IORESOURCE_BUSY | IORESOURCE_MEM
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};
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extern void efi_initialize_iomem_resources(struct resource *,
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struct resource *);
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extern char _text[], _end[], _etext[];
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unsigned long ia64_max_cacheline_size;
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int dma_get_cache_alignment(void)
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{
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return ia64_max_cacheline_size;
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}
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EXPORT_SYMBOL(dma_get_cache_alignment);
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unsigned long ia64_iobase; /* virtual address for I/O accesses */
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EXPORT_SYMBOL(ia64_iobase);
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struct io_space io_space[MAX_IO_SPACES];
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EXPORT_SYMBOL(io_space);
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unsigned int num_io_spaces;
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/*
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* "flush_icache_range()" needs to know what processor dependent stride size to use
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* when it makes i-cache(s) coherent with d-caches.
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*/
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#define I_CACHE_STRIDE_SHIFT 5 /* Safest way to go: 32 bytes by 32 bytes */
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unsigned long ia64_i_cache_stride_shift = ~0;
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/*
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* The merge_mask variable needs to be set to (max(iommu_page_size(iommu)) - 1). This
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* mask specifies a mask of address bits that must be 0 in order for two buffers to be
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* mergeable by the I/O MMU (i.e., the end address of the first buffer and the start
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* address of the second buffer must be aligned to (merge_mask+1) in order to be
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* mergeable). By default, we assume there is no I/O MMU which can merge physically
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* discontiguous buffers, so we set the merge_mask to ~0UL, which corresponds to a iommu
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* page-size of 2^64.
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*/
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unsigned long ia64_max_iommu_merge_mask = ~0UL;
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EXPORT_SYMBOL(ia64_max_iommu_merge_mask);
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/*
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* We use a special marker for the end of memory and it uses the extra (+1) slot
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*/
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struct rsvd_region rsvd_region[IA64_MAX_RSVD_REGIONS + 1] __initdata;
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int num_rsvd_regions __initdata;
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/*
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* Filter incoming memory segments based on the primitive map created from the boot
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* parameters. Segments contained in the map are removed from the memory ranges. A
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* caller-specified function is called with the memory ranges that remain after filtering.
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* This routine does not assume the incoming segments are sorted.
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*/
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int __init
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filter_rsvd_memory (unsigned long start, unsigned long end, void *arg)
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{
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unsigned long range_start, range_end, prev_start;
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void (*func)(unsigned long, unsigned long, int);
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int i;
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#if IGNORE_PFN0
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if (start == PAGE_OFFSET) {
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printk(KERN_WARNING "warning: skipping physical page 0\n");
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start += PAGE_SIZE;
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if (start >= end) return 0;
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}
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#endif
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/*
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* lowest possible address(walker uses virtual)
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*/
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prev_start = PAGE_OFFSET;
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func = arg;
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for (i = 0; i < num_rsvd_regions; ++i) {
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range_start = max(start, prev_start);
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range_end = min(end, rsvd_region[i].start);
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if (range_start < range_end)
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call_pernode_memory(__pa(range_start), range_end - range_start, func);
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/* nothing more available in this segment */
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if (range_end == end) return 0;
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prev_start = rsvd_region[i].end;
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}
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/* end of memory marker allows full processing inside loop body */
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return 0;
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}
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static void __init
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sort_regions (struct rsvd_region *rsvd_region, int max)
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{
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int j;
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/* simple bubble sorting */
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while (max--) {
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for (j = 0; j < max; ++j) {
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if (rsvd_region[j].start > rsvd_region[j+1].start) {
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struct rsvd_region tmp;
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tmp = rsvd_region[j];
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rsvd_region[j] = rsvd_region[j + 1];
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rsvd_region[j + 1] = tmp;
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}
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}
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}
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}
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/*
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* Request address space for all standard resources
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*/
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static int __init register_memory(void)
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{
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code_resource.start = ia64_tpa(_text);
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code_resource.end = ia64_tpa(_etext) - 1;
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data_resource.start = ia64_tpa(_etext);
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data_resource.end = ia64_tpa(_end) - 1;
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efi_initialize_iomem_resources(&code_resource, &data_resource);
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return 0;
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}
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__initcall(register_memory);
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/**
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* reserve_memory - setup reserved memory areas
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*
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* Setup the reserved memory areas set aside for the boot parameters,
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* initrd, etc. There are currently %IA64_MAX_RSVD_REGIONS defined,
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* see include/asm-ia64/meminit.h if you need to define more.
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*/
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void __init
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reserve_memory (void)
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{
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int n = 0;
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/*
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* none of the entries in this table overlap
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*/
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rsvd_region[n].start = (unsigned long) ia64_boot_param;
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rsvd_region[n].end = rsvd_region[n].start + sizeof(*ia64_boot_param);
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n++;
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rsvd_region[n].start = (unsigned long) __va(ia64_boot_param->efi_memmap);
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rsvd_region[n].end = rsvd_region[n].start + ia64_boot_param->efi_memmap_size;
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n++;
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rsvd_region[n].start = (unsigned long) __va(ia64_boot_param->command_line);
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rsvd_region[n].end = (rsvd_region[n].start
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+ strlen(__va(ia64_boot_param->command_line)) + 1);
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n++;
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rsvd_region[n].start = (unsigned long) ia64_imva((void *)KERNEL_START);
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rsvd_region[n].end = (unsigned long) ia64_imva(_end);
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n++;
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#ifdef CONFIG_BLK_DEV_INITRD
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if (ia64_boot_param->initrd_start) {
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rsvd_region[n].start = (unsigned long)__va(ia64_boot_param->initrd_start);
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rsvd_region[n].end = rsvd_region[n].start + ia64_boot_param->initrd_size;
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n++;
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}
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#endif
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efi_memmap_init(&rsvd_region[n].start, &rsvd_region[n].end);
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n++;
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/* end of memory marker */
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rsvd_region[n].start = ~0UL;
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rsvd_region[n].end = ~0UL;
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n++;
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num_rsvd_regions = n;
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BUG_ON(IA64_MAX_RSVD_REGIONS + 1 < n);
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sort_regions(rsvd_region, num_rsvd_regions);
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}
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/**
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* find_initrd - get initrd parameters from the boot parameter structure
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*
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* Grab the initrd start and end from the boot parameter struct given us by
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* the boot loader.
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*/
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void __init
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find_initrd (void)
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{
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#ifdef CONFIG_BLK_DEV_INITRD
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if (ia64_boot_param->initrd_start) {
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initrd_start = (unsigned long)__va(ia64_boot_param->initrd_start);
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initrd_end = initrd_start+ia64_boot_param->initrd_size;
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printk(KERN_INFO "Initial ramdisk at: 0x%lx (%lu bytes)\n",
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initrd_start, ia64_boot_param->initrd_size);
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}
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#endif
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}
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static void __init
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io_port_init (void)
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{
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unsigned long phys_iobase;
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/*
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* Set `iobase' based on the EFI memory map or, failing that, the
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* value firmware left in ar.k0.
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*
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* Note that in ia32 mode, IN/OUT instructions use ar.k0 to compute
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* the port's virtual address, so ia32_load_state() loads it with a
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* user virtual address. But in ia64 mode, glibc uses the
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* *physical* address in ar.k0 to mmap the appropriate area from
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* /dev/mem, and the inX()/outX() interfaces use MMIO. In both
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* cases, user-mode can only use the legacy 0-64K I/O port space.
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*
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* ar.k0 is not involved in kernel I/O port accesses, which can use
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* any of the I/O port spaces and are done via MMIO using the
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* virtual mmio_base from the appropriate io_space[].
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*/
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phys_iobase = efi_get_iobase();
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if (!phys_iobase) {
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phys_iobase = ia64_get_kr(IA64_KR_IO_BASE);
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printk(KERN_INFO "No I/O port range found in EFI memory map, "
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"falling back to AR.KR0 (0x%lx)\n", phys_iobase);
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}
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ia64_iobase = (unsigned long) ioremap(phys_iobase, 0);
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ia64_set_kr(IA64_KR_IO_BASE, __pa(ia64_iobase));
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/* setup legacy IO port space */
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io_space[0].mmio_base = ia64_iobase;
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io_space[0].sparse = 1;
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num_io_spaces = 1;
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}
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/**
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* early_console_setup - setup debugging console
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*
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* Consoles started here require little enough setup that we can start using
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* them very early in the boot process, either right after the machine
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* vector initialization, or even before if the drivers can detect their hw.
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*
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* Returns non-zero if a console couldn't be setup.
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*/
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static inline int __init
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early_console_setup (char *cmdline)
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{
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int earlycons = 0;
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#ifdef CONFIG_SERIAL_SGI_L1_CONSOLE
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{
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extern int sn_serial_console_early_setup(void);
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if (!sn_serial_console_early_setup())
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earlycons++;
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}
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#endif
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#ifdef CONFIG_EFI_PCDP
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if (!efi_setup_pcdp_console(cmdline))
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earlycons++;
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#endif
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#ifdef CONFIG_SERIAL_8250_CONSOLE
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if (!early_serial_console_init(cmdline))
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earlycons++;
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#endif
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return (earlycons) ? 0 : -1;
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}
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static inline void
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mark_bsp_online (void)
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{
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#ifdef CONFIG_SMP
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/* If we register an early console, allow CPU 0 to printk */
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cpu_set(smp_processor_id(), cpu_online_map);
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#endif
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}
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#ifdef CONFIG_SMP
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static void __init
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check_for_logical_procs (void)
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{
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pal_logical_to_physical_t info;
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s64 status;
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status = ia64_pal_logical_to_phys(0, &info);
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if (status == -1) {
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printk(KERN_INFO "No logical to physical processor mapping "
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"available\n");
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return;
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}
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if (status) {
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printk(KERN_ERR "ia64_pal_logical_to_phys failed with %ld\n",
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status);
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return;
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}
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/*
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* Total number of siblings that BSP has. Though not all of them
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* may have booted successfully. The correct number of siblings
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* booted is in info.overview_num_log.
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*/
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smp_num_siblings = info.overview_tpc;
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smp_num_cpucores = info.overview_cpp;
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}
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#endif
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static __initdata int nomca;
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static __init int setup_nomca(char *s)
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{
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nomca = 1;
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return 0;
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}
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early_param("nomca", setup_nomca);
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void __init
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setup_arch (char **cmdline_p)
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{
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unw_init();
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ia64_patch_vtop((u64) __start___vtop_patchlist, (u64) __end___vtop_patchlist);
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*cmdline_p = __va(ia64_boot_param->command_line);
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strlcpy(saved_command_line, *cmdline_p, COMMAND_LINE_SIZE);
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efi_init();
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io_port_init();
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parse_early_param();
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#ifdef CONFIG_IA64_GENERIC
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machvec_init(NULL);
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#endif
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if (early_console_setup(*cmdline_p) == 0)
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mark_bsp_online();
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#ifdef CONFIG_ACPI
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/* Initialize the ACPI boot-time table parser */
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acpi_table_init();
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# ifdef CONFIG_ACPI_NUMA
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acpi_numa_init();
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# endif
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#else
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# ifdef CONFIG_SMP
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smp_build_cpu_map(); /* happens, e.g., with the Ski simulator */
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# endif
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#endif /* CONFIG_APCI_BOOT */
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find_memory();
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/* process SAL system table: */
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ia64_sal_init(__va(efi.sal_systab));
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ia64_setup_printk_clock();
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#ifdef CONFIG_SMP
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cpu_physical_id(0) = hard_smp_processor_id();
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cpu_set(0, cpu_sibling_map[0]);
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cpu_set(0, cpu_core_map[0]);
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check_for_logical_procs();
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if (smp_num_cpucores > 1)
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printk(KERN_INFO
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"cpu package is Multi-Core capable: number of cores=%d\n",
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smp_num_cpucores);
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if (smp_num_siblings > 1)
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printk(KERN_INFO
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"cpu package is Multi-Threading capable: number of siblings=%d\n",
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smp_num_siblings);
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#endif
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cpu_init(); /* initialize the bootstrap CPU */
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mmu_context_init(); /* initialize context_id bitmap */
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#ifdef CONFIG_ACPI
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acpi_boot_init();
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#endif
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#ifdef CONFIG_VT
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if (!conswitchp) {
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# if defined(CONFIG_DUMMY_CONSOLE)
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conswitchp = &dummy_con;
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# endif
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# if defined(CONFIG_VGA_CONSOLE)
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/*
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* Non-legacy systems may route legacy VGA MMIO range to system
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* memory. vga_con probes the MMIO hole, so memory looks like
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* a VGA device to it. The EFI memory map can tell us if it's
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* memory so we can avoid this problem.
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*/
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if (efi_mem_type(0xA0000) != EFI_CONVENTIONAL_MEMORY)
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conswitchp = &vga_con;
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# endif
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}
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#endif
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/* enable IA-64 Machine Check Abort Handling unless disabled */
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if (!nomca)
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ia64_mca_init();
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platform_setup(cmdline_p);
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paging_init();
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}
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/*
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* Display cpu info for all cpu's.
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*/
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static int
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show_cpuinfo (struct seq_file *m, void *v)
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{
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#ifdef CONFIG_SMP
|
|
# define lpj c->loops_per_jiffy
|
|
# define cpunum c->cpu
|
|
#else
|
|
# define lpj loops_per_jiffy
|
|
# define cpunum 0
|
|
#endif
|
|
static struct {
|
|
unsigned long mask;
|
|
const char *feature_name;
|
|
} feature_bits[] = {
|
|
{ 1UL << 0, "branchlong" },
|
|
{ 1UL << 1, "spontaneous deferral"},
|
|
{ 1UL << 2, "16-byte atomic ops" }
|
|
};
|
|
char family[32], features[128], *cp, sep;
|
|
struct cpuinfo_ia64 *c = v;
|
|
unsigned long mask;
|
|
unsigned long proc_freq;
|
|
int i;
|
|
|
|
mask = c->features;
|
|
|
|
switch (c->family) {
|
|
case 0x07: memcpy(family, "Itanium", 8); break;
|
|
case 0x1f: memcpy(family, "Itanium 2", 10); break;
|
|
default: sprintf(family, "%u", c->family); break;
|
|
}
|
|
|
|
/* build the feature string: */
|
|
memcpy(features, " standard", 10);
|
|
cp = features;
|
|
sep = 0;
|
|
for (i = 0; i < (int) ARRAY_SIZE(feature_bits); ++i) {
|
|
if (mask & feature_bits[i].mask) {
|
|
if (sep)
|
|
*cp++ = sep;
|
|
sep = ',';
|
|
*cp++ = ' ';
|
|
strcpy(cp, feature_bits[i].feature_name);
|
|
cp += strlen(feature_bits[i].feature_name);
|
|
mask &= ~feature_bits[i].mask;
|
|
}
|
|
}
|
|
if (mask) {
|
|
/* print unknown features as a hex value: */
|
|
if (sep)
|
|
*cp++ = sep;
|
|
sprintf(cp, " 0x%lx", mask);
|
|
}
|
|
|
|
proc_freq = cpufreq_quick_get(cpunum);
|
|
if (!proc_freq)
|
|
proc_freq = c->proc_freq / 1000;
|
|
|
|
seq_printf(m,
|
|
"processor : %d\n"
|
|
"vendor : %s\n"
|
|
"arch : IA-64\n"
|
|
"family : %s\n"
|
|
"model : %u\n"
|
|
"revision : %u\n"
|
|
"archrev : %u\n"
|
|
"features :%s\n" /* don't change this---it _is_ right! */
|
|
"cpu number : %lu\n"
|
|
"cpu regs : %u\n"
|
|
"cpu MHz : %lu.%06lu\n"
|
|
"itc MHz : %lu.%06lu\n"
|
|
"BogoMIPS : %lu.%02lu\n",
|
|
cpunum, c->vendor, family, c->model, c->revision, c->archrev,
|
|
features, c->ppn, c->number,
|
|
proc_freq / 1000, proc_freq % 1000,
|
|
c->itc_freq / 1000000, c->itc_freq % 1000000,
|
|
lpj*HZ/500000, (lpj*HZ/5000) % 100);
|
|
#ifdef CONFIG_SMP
|
|
seq_printf(m, "siblings : %u\n", cpus_weight(cpu_core_map[cpunum]));
|
|
if (c->threads_per_core > 1 || c->cores_per_socket > 1)
|
|
seq_printf(m,
|
|
"physical id: %u\n"
|
|
"core id : %u\n"
|
|
"thread id : %u\n",
|
|
c->socket_id, c->core_id, c->thread_id);
|
|
#endif
|
|
seq_printf(m,"\n");
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void *
|
|
c_start (struct seq_file *m, loff_t *pos)
|
|
{
|
|
#ifdef CONFIG_SMP
|
|
while (*pos < NR_CPUS && !cpu_isset(*pos, cpu_online_map))
|
|
++*pos;
|
|
#endif
|
|
return *pos < NR_CPUS ? cpu_data(*pos) : NULL;
|
|
}
|
|
|
|
static void *
|
|
c_next (struct seq_file *m, void *v, loff_t *pos)
|
|
{
|
|
++*pos;
|
|
return c_start(m, pos);
|
|
}
|
|
|
|
static void
|
|
c_stop (struct seq_file *m, void *v)
|
|
{
|
|
}
|
|
|
|
struct seq_operations cpuinfo_op = {
|
|
.start = c_start,
|
|
.next = c_next,
|
|
.stop = c_stop,
|
|
.show = show_cpuinfo
|
|
};
|
|
|
|
static void __cpuinit
|
|
identify_cpu (struct cpuinfo_ia64 *c)
|
|
{
|
|
union {
|
|
unsigned long bits[5];
|
|
struct {
|
|
/* id 0 & 1: */
|
|
char vendor[16];
|
|
|
|
/* id 2 */
|
|
u64 ppn; /* processor serial number */
|
|
|
|
/* id 3: */
|
|
unsigned number : 8;
|
|
unsigned revision : 8;
|
|
unsigned model : 8;
|
|
unsigned family : 8;
|
|
unsigned archrev : 8;
|
|
unsigned reserved : 24;
|
|
|
|
/* id 4: */
|
|
u64 features;
|
|
} field;
|
|
} cpuid;
|
|
pal_vm_info_1_u_t vm1;
|
|
pal_vm_info_2_u_t vm2;
|
|
pal_status_t status;
|
|
unsigned long impl_va_msb = 50, phys_addr_size = 44; /* Itanium defaults */
|
|
int i;
|
|
|
|
for (i = 0; i < 5; ++i)
|
|
cpuid.bits[i] = ia64_get_cpuid(i);
|
|
|
|
memcpy(c->vendor, cpuid.field.vendor, 16);
|
|
#ifdef CONFIG_SMP
|
|
c->cpu = smp_processor_id();
|
|
|
|
/* below default values will be overwritten by identify_siblings()
|
|
* for Multi-Threading/Multi-Core capable cpu's
|
|
*/
|
|
c->threads_per_core = c->cores_per_socket = c->num_log = 1;
|
|
c->socket_id = -1;
|
|
|
|
identify_siblings(c);
|
|
#endif
|
|
c->ppn = cpuid.field.ppn;
|
|
c->number = cpuid.field.number;
|
|
c->revision = cpuid.field.revision;
|
|
c->model = cpuid.field.model;
|
|
c->family = cpuid.field.family;
|
|
c->archrev = cpuid.field.archrev;
|
|
c->features = cpuid.field.features;
|
|
|
|
status = ia64_pal_vm_summary(&vm1, &vm2);
|
|
if (status == PAL_STATUS_SUCCESS) {
|
|
impl_va_msb = vm2.pal_vm_info_2_s.impl_va_msb;
|
|
phys_addr_size = vm1.pal_vm_info_1_s.phys_add_size;
|
|
}
|
|
c->unimpl_va_mask = ~((7L<<61) | ((1L << (impl_va_msb + 1)) - 1));
|
|
c->unimpl_pa_mask = ~((1L<<63) | ((1L << phys_addr_size) - 1));
|
|
}
|
|
|
|
void
|
|
setup_per_cpu_areas (void)
|
|
{
|
|
/* start_kernel() requires this... */
|
|
#ifdef CONFIG_ACPI_HOTPLUG_CPU
|
|
prefill_possible_map();
|
|
#endif
|
|
}
|
|
|
|
/*
|
|
* Calculate the max. cache line size.
|
|
*
|
|
* In addition, the minimum of the i-cache stride sizes is calculated for
|
|
* "flush_icache_range()".
|
|
*/
|
|
static void __cpuinit
|
|
get_max_cacheline_size (void)
|
|
{
|
|
unsigned long line_size, max = 1;
|
|
unsigned int cache_size = 0;
|
|
u64 l, levels, unique_caches;
|
|
pal_cache_config_info_t cci;
|
|
s64 status;
|
|
|
|
status = ia64_pal_cache_summary(&levels, &unique_caches);
|
|
if (status != 0) {
|
|
printk(KERN_ERR "%s: ia64_pal_cache_summary() failed (status=%ld)\n",
|
|
__FUNCTION__, status);
|
|
max = SMP_CACHE_BYTES;
|
|
/* Safest setup for "flush_icache_range()" */
|
|
ia64_i_cache_stride_shift = I_CACHE_STRIDE_SHIFT;
|
|
goto out;
|
|
}
|
|
|
|
for (l = 0; l < levels; ++l) {
|
|
status = ia64_pal_cache_config_info(l, /* cache_type (data_or_unified)= */ 2,
|
|
&cci);
|
|
if (status != 0) {
|
|
printk(KERN_ERR
|
|
"%s: ia64_pal_cache_config_info(l=%lu, 2) failed (status=%ld)\n",
|
|
__FUNCTION__, l, status);
|
|
max = SMP_CACHE_BYTES;
|
|
/* The safest setup for "flush_icache_range()" */
|
|
cci.pcci_stride = I_CACHE_STRIDE_SHIFT;
|
|
cci.pcci_unified = 1;
|
|
}
|
|
line_size = 1 << cci.pcci_line_size;
|
|
if (line_size > max)
|
|
max = line_size;
|
|
if (cache_size < cci.pcci_cache_size)
|
|
cache_size = cci.pcci_cache_size;
|
|
if (!cci.pcci_unified) {
|
|
status = ia64_pal_cache_config_info(l,
|
|
/* cache_type (instruction)= */ 1,
|
|
&cci);
|
|
if (status != 0) {
|
|
printk(KERN_ERR
|
|
"%s: ia64_pal_cache_config_info(l=%lu, 1) failed (status=%ld)\n",
|
|
__FUNCTION__, l, status);
|
|
/* The safest setup for "flush_icache_range()" */
|
|
cci.pcci_stride = I_CACHE_STRIDE_SHIFT;
|
|
}
|
|
}
|
|
if (cci.pcci_stride < ia64_i_cache_stride_shift)
|
|
ia64_i_cache_stride_shift = cci.pcci_stride;
|
|
}
|
|
out:
|
|
#ifdef CONFIG_SMP
|
|
max_cache_size = max(max_cache_size, cache_size);
|
|
#endif
|
|
if (max > ia64_max_cacheline_size)
|
|
ia64_max_cacheline_size = max;
|
|
}
|
|
|
|
/*
|
|
* cpu_init() initializes state that is per-CPU. This function acts
|
|
* as a 'CPU state barrier', nothing should get across.
|
|
*/
|
|
void __cpuinit
|
|
cpu_init (void)
|
|
{
|
|
extern void __cpuinit ia64_mmu_init (void *);
|
|
unsigned long num_phys_stacked;
|
|
pal_vm_info_2_u_t vmi;
|
|
unsigned int max_ctx;
|
|
struct cpuinfo_ia64 *cpu_info;
|
|
void *cpu_data;
|
|
|
|
cpu_data = per_cpu_init();
|
|
|
|
/*
|
|
* We set ar.k3 so that assembly code in MCA handler can compute
|
|
* physical addresses of per cpu variables with a simple:
|
|
* phys = ar.k3 + &per_cpu_var
|
|
*/
|
|
ia64_set_kr(IA64_KR_PER_CPU_DATA,
|
|
ia64_tpa(cpu_data) - (long) __per_cpu_start);
|
|
|
|
get_max_cacheline_size();
|
|
|
|
/*
|
|
* We can't pass "local_cpu_data" to identify_cpu() because we haven't called
|
|
* ia64_mmu_init() yet. And we can't call ia64_mmu_init() first because it
|
|
* depends on the data returned by identify_cpu(). We break the dependency by
|
|
* accessing cpu_data() through the canonical per-CPU address.
|
|
*/
|
|
cpu_info = cpu_data + ((char *) &__ia64_per_cpu_var(cpu_info) - __per_cpu_start);
|
|
identify_cpu(cpu_info);
|
|
|
|
#ifdef CONFIG_MCKINLEY
|
|
{
|
|
# define FEATURE_SET 16
|
|
struct ia64_pal_retval iprv;
|
|
|
|
if (cpu_info->family == 0x1f) {
|
|
PAL_CALL_PHYS(iprv, PAL_PROC_GET_FEATURES, 0, FEATURE_SET, 0);
|
|
if ((iprv.status == 0) && (iprv.v0 & 0x80) && (iprv.v2 & 0x80))
|
|
PAL_CALL_PHYS(iprv, PAL_PROC_SET_FEATURES,
|
|
(iprv.v1 | 0x80), FEATURE_SET, 0);
|
|
}
|
|
}
|
|
#endif
|
|
|
|
/* Clear the stack memory reserved for pt_regs: */
|
|
memset(task_pt_regs(current), 0, sizeof(struct pt_regs));
|
|
|
|
ia64_set_kr(IA64_KR_FPU_OWNER, 0);
|
|
|
|
/*
|
|
* Initialize the page-table base register to a global
|
|
* directory with all zeroes. This ensure that we can handle
|
|
* TLB-misses to user address-space even before we created the
|
|
* first user address-space. This may happen, e.g., due to
|
|
* aggressive use of lfetch.fault.
|
|
*/
|
|
ia64_set_kr(IA64_KR_PT_BASE, __pa(ia64_imva(empty_zero_page)));
|
|
|
|
/*
|
|
* Initialize default control register to defer speculative faults except
|
|
* for those arising from TLB misses, which are not deferred. The
|
|
* kernel MUST NOT depend on a particular setting of these bits (in other words,
|
|
* the kernel must have recovery code for all speculative accesses). Turn on
|
|
* dcr.lc as per recommendation by the architecture team. Most IA-32 apps
|
|
* shouldn't be affected by this (moral: keep your ia32 locks aligned and you'll
|
|
* be fine).
|
|
*/
|
|
ia64_setreg(_IA64_REG_CR_DCR, ( IA64_DCR_DP | IA64_DCR_DK | IA64_DCR_DX | IA64_DCR_DR
|
|
| IA64_DCR_DA | IA64_DCR_DD | IA64_DCR_LC));
|
|
atomic_inc(&init_mm.mm_count);
|
|
current->active_mm = &init_mm;
|
|
if (current->mm)
|
|
BUG();
|
|
|
|
ia64_mmu_init(ia64_imva(cpu_data));
|
|
ia64_mca_cpu_init(ia64_imva(cpu_data));
|
|
|
|
#ifdef CONFIG_IA32_SUPPORT
|
|
ia32_cpu_init();
|
|
#endif
|
|
|
|
/* Clear ITC to eliminiate sched_clock() overflows in human time. */
|
|
ia64_set_itc(0);
|
|
|
|
/* disable all local interrupt sources: */
|
|
ia64_set_itv(1 << 16);
|
|
ia64_set_lrr0(1 << 16);
|
|
ia64_set_lrr1(1 << 16);
|
|
ia64_setreg(_IA64_REG_CR_PMV, 1 << 16);
|
|
ia64_setreg(_IA64_REG_CR_CMCV, 1 << 16);
|
|
|
|
/* clear TPR & XTP to enable all interrupt classes: */
|
|
ia64_setreg(_IA64_REG_CR_TPR, 0);
|
|
#ifdef CONFIG_SMP
|
|
normal_xtp();
|
|
#endif
|
|
|
|
/* set ia64_ctx.max_rid to the maximum RID that is supported by all CPUs: */
|
|
if (ia64_pal_vm_summary(NULL, &vmi) == 0)
|
|
max_ctx = (1U << (vmi.pal_vm_info_2_s.rid_size - 3)) - 1;
|
|
else {
|
|
printk(KERN_WARNING "cpu_init: PAL VM summary failed, assuming 18 RID bits\n");
|
|
max_ctx = (1U << 15) - 1; /* use architected minimum */
|
|
}
|
|
while (max_ctx < ia64_ctx.max_ctx) {
|
|
unsigned int old = ia64_ctx.max_ctx;
|
|
if (cmpxchg(&ia64_ctx.max_ctx, old, max_ctx) == old)
|
|
break;
|
|
}
|
|
|
|
if (ia64_pal_rse_info(&num_phys_stacked, NULL) != 0) {
|
|
printk(KERN_WARNING "cpu_init: PAL RSE info failed; assuming 96 physical "
|
|
"stacked regs\n");
|
|
num_phys_stacked = 96;
|
|
}
|
|
/* size of physical stacked register partition plus 8 bytes: */
|
|
__get_cpu_var(ia64_phys_stacked_size_p8) = num_phys_stacked*8 + 8;
|
|
platform_cpu_init();
|
|
pm_idle = default_idle;
|
|
}
|
|
|
|
/*
|
|
* On SMP systems, when the scheduler does migration-cost autodetection,
|
|
* it needs a way to flush as much of the CPU's caches as possible.
|
|
*/
|
|
void sched_cacheflush(void)
|
|
{
|
|
ia64_sal_cache_flush(3);
|
|
}
|
|
|
|
void __init
|
|
check_bugs (void)
|
|
{
|
|
ia64_patch_mckinley_e9((unsigned long) __start___mckinley_e9_bundles,
|
|
(unsigned long) __end___mckinley_e9_bundles);
|
|
}
|
|
|
|
static int __init run_dmi_scan(void)
|
|
{
|
|
dmi_scan_machine();
|
|
return 0;
|
|
}
|
|
core_initcall(run_dmi_scan);
|