498 lines
12 KiB
C
498 lines
12 KiB
C
/*
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* Real Time Clock interface for XScale PXA27x and PXA3xx
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*
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* Copyright (C) 2008 Robert Jarzmik
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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*/
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <linux/module.h>
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#include <linux/rtc.h>
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#include <linux/seq_file.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/slab.h>
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#include <mach/hardware.h>
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#define TIMER_FREQ CLOCK_TICK_RATE
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#define RTC_DEF_DIVIDER (32768 - 1)
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#define RTC_DEF_TRIM 0
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#define MAXFREQ_PERIODIC 1000
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/*
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* PXA Registers and bits definitions
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*/
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#define RTSR_PICE (1 << 15) /* Periodic interrupt count enable */
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#define RTSR_PIALE (1 << 14) /* Periodic interrupt Alarm enable */
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#define RTSR_PIAL (1 << 13) /* Periodic interrupt detected */
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#define RTSR_SWALE2 (1 << 11) /* RTC stopwatch alarm2 enable */
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#define RTSR_SWAL2 (1 << 10) /* RTC stopwatch alarm2 detected */
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#define RTSR_SWALE1 (1 << 9) /* RTC stopwatch alarm1 enable */
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#define RTSR_SWAL1 (1 << 8) /* RTC stopwatch alarm1 detected */
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#define RTSR_RDALE2 (1 << 7) /* RTC alarm2 enable */
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#define RTSR_RDAL2 (1 << 6) /* RTC alarm2 detected */
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#define RTSR_RDALE1 (1 << 5) /* RTC alarm1 enable */
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#define RTSR_RDAL1 (1 << 4) /* RTC alarm1 detected */
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#define RTSR_HZE (1 << 3) /* HZ interrupt enable */
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#define RTSR_ALE (1 << 2) /* RTC alarm interrupt enable */
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#define RTSR_HZ (1 << 1) /* HZ rising-edge detected */
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#define RTSR_AL (1 << 0) /* RTC alarm detected */
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#define RTSR_TRIG_MASK (RTSR_AL | RTSR_HZ | RTSR_RDAL1 | RTSR_RDAL2\
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| RTSR_SWAL1 | RTSR_SWAL2)
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#define RYxR_YEAR_S 9
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#define RYxR_YEAR_MASK (0xfff << RYxR_YEAR_S)
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#define RYxR_MONTH_S 5
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#define RYxR_MONTH_MASK (0xf << RYxR_MONTH_S)
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#define RYxR_DAY_MASK 0x1f
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#define RDxR_HOUR_S 12
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#define RDxR_HOUR_MASK (0x1f << RDxR_HOUR_S)
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#define RDxR_MIN_S 6
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#define RDxR_MIN_MASK (0x3f << RDxR_MIN_S)
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#define RDxR_SEC_MASK 0x3f
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#define RTSR 0x08
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#define RTTR 0x0c
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#define RDCR 0x10
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#define RYCR 0x14
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#define RDAR1 0x18
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#define RYAR1 0x1c
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#define RTCPICR 0x34
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#define PIAR 0x38
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#define rtc_readl(pxa_rtc, reg) \
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__raw_readl((pxa_rtc)->base + (reg))
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#define rtc_writel(pxa_rtc, reg, value) \
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__raw_writel((value), (pxa_rtc)->base + (reg))
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struct pxa_rtc {
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struct resource *ress;
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void __iomem *base;
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int irq_1Hz;
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int irq_Alrm;
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struct rtc_device *rtc;
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spinlock_t lock; /* Protects this structure */
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};
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static u32 ryxr_calc(struct rtc_time *tm)
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{
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return ((tm->tm_year + 1900) << RYxR_YEAR_S)
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| ((tm->tm_mon + 1) << RYxR_MONTH_S)
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| tm->tm_mday;
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}
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static u32 rdxr_calc(struct rtc_time *tm)
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{
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return (tm->tm_hour << RDxR_HOUR_S) | (tm->tm_min << RDxR_MIN_S)
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| tm->tm_sec;
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}
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static void tm_calc(u32 rycr, u32 rdcr, struct rtc_time *tm)
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{
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tm->tm_year = ((rycr & RYxR_YEAR_MASK) >> RYxR_YEAR_S) - 1900;
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tm->tm_mon = (((rycr & RYxR_MONTH_MASK) >> RYxR_MONTH_S)) - 1;
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tm->tm_mday = (rycr & RYxR_DAY_MASK);
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tm->tm_hour = (rdcr & RDxR_HOUR_MASK) >> RDxR_HOUR_S;
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tm->tm_min = (rdcr & RDxR_MIN_MASK) >> RDxR_MIN_S;
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tm->tm_sec = rdcr & RDxR_SEC_MASK;
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}
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static void rtsr_clear_bits(struct pxa_rtc *pxa_rtc, u32 mask)
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{
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u32 rtsr;
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rtsr = rtc_readl(pxa_rtc, RTSR);
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rtsr &= ~RTSR_TRIG_MASK;
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rtsr &= ~mask;
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rtc_writel(pxa_rtc, RTSR, rtsr);
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}
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static void rtsr_set_bits(struct pxa_rtc *pxa_rtc, u32 mask)
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{
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u32 rtsr;
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rtsr = rtc_readl(pxa_rtc, RTSR);
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rtsr &= ~RTSR_TRIG_MASK;
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rtsr |= mask;
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rtc_writel(pxa_rtc, RTSR, rtsr);
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}
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static irqreturn_t pxa_rtc_irq(int irq, void *dev_id)
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{
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struct platform_device *pdev = to_platform_device(dev_id);
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struct pxa_rtc *pxa_rtc = platform_get_drvdata(pdev);
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u32 rtsr;
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unsigned long events = 0;
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spin_lock(&pxa_rtc->lock);
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/* clear interrupt sources */
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rtsr = rtc_readl(pxa_rtc, RTSR);
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rtc_writel(pxa_rtc, RTSR, rtsr);
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/* temporary disable rtc interrupts */
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rtsr_clear_bits(pxa_rtc, RTSR_RDALE1 | RTSR_PIALE | RTSR_HZE);
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/* clear alarm interrupt if it has occurred */
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if (rtsr & RTSR_RDAL1)
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rtsr &= ~RTSR_RDALE1;
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/* update irq data & counter */
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if (rtsr & RTSR_RDAL1)
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events |= RTC_AF | RTC_IRQF;
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if (rtsr & RTSR_HZ)
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events |= RTC_UF | RTC_IRQF;
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if (rtsr & RTSR_PIAL)
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events |= RTC_PF | RTC_IRQF;
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rtc_update_irq(pxa_rtc->rtc, 1, events);
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/* enable back rtc interrupts */
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rtc_writel(pxa_rtc, RTSR, rtsr & ~RTSR_TRIG_MASK);
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spin_unlock(&pxa_rtc->lock);
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return IRQ_HANDLED;
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}
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static int pxa_rtc_open(struct device *dev)
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{
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struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
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int ret;
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ret = request_irq(pxa_rtc->irq_1Hz, pxa_rtc_irq, IRQF_DISABLED,
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"rtc 1Hz", dev);
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if (ret < 0) {
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dev_err(dev, "can't get irq %i, err %d\n", pxa_rtc->irq_1Hz,
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ret);
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goto err_irq_1Hz;
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}
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ret = request_irq(pxa_rtc->irq_Alrm, pxa_rtc_irq, IRQF_DISABLED,
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"rtc Alrm", dev);
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if (ret < 0) {
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dev_err(dev, "can't get irq %i, err %d\n", pxa_rtc->irq_Alrm,
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ret);
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goto err_irq_Alrm;
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}
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return 0;
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err_irq_Alrm:
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free_irq(pxa_rtc->irq_1Hz, dev);
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err_irq_1Hz:
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return ret;
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}
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static void pxa_rtc_release(struct device *dev)
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{
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struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
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spin_lock_irq(&pxa_rtc->lock);
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rtsr_clear_bits(pxa_rtc, RTSR_PIALE | RTSR_RDALE1 | RTSR_HZE);
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spin_unlock_irq(&pxa_rtc->lock);
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free_irq(pxa_rtc->irq_Alrm, dev);
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free_irq(pxa_rtc->irq_1Hz, dev);
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}
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static int pxa_periodic_irq_set_freq(struct device *dev, int freq)
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{
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struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
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int period_ms;
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if (freq < 1 || freq > MAXFREQ_PERIODIC)
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return -EINVAL;
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period_ms = 1000 / freq;
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rtc_writel(pxa_rtc, PIAR, period_ms);
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return 0;
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}
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static int pxa_periodic_irq_set_state(struct device *dev, int enabled)
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{
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struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
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if (enabled)
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rtsr_set_bits(pxa_rtc, RTSR_PIALE | RTSR_PICE);
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else
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rtsr_clear_bits(pxa_rtc, RTSR_PIALE | RTSR_PICE);
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return 0;
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}
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static int pxa_alarm_irq_enable(struct device *dev, unsigned int enabled)
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{
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struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
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spin_lock_irq(&pxa_rtc->lock);
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if (enabled)
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rtsr_set_bits(pxa_rtc, RTSR_RDALE1);
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else
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rtsr_clear_bits(pxa_rtc, RTSR_RDALE1);
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spin_unlock_irq(&pxa_rtc->lock);
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return 0;
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}
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static int pxa_update_irq_enable(struct device *dev, unsigned int enabled)
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{
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struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
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spin_lock_irq(&pxa_rtc->lock);
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if (enabled)
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rtsr_set_bits(pxa_rtc, RTSR_HZE);
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else
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rtsr_clear_bits(pxa_rtc, RTSR_HZE);
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spin_unlock_irq(&pxa_rtc->lock);
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return 0;
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}
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static int pxa_rtc_read_time(struct device *dev, struct rtc_time *tm)
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{
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struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
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u32 rycr, rdcr;
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rycr = rtc_readl(pxa_rtc, RYCR);
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rdcr = rtc_readl(pxa_rtc, RDCR);
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tm_calc(rycr, rdcr, tm);
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return 0;
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}
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static int pxa_rtc_set_time(struct device *dev, struct rtc_time *tm)
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{
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struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
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rtc_writel(pxa_rtc, RYCR, ryxr_calc(tm));
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rtc_writel(pxa_rtc, RDCR, rdxr_calc(tm));
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return 0;
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}
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static int pxa_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
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{
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struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
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u32 rtsr, ryar, rdar;
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ryar = rtc_readl(pxa_rtc, RYAR1);
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rdar = rtc_readl(pxa_rtc, RDAR1);
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tm_calc(ryar, rdar, &alrm->time);
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rtsr = rtc_readl(pxa_rtc, RTSR);
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alrm->enabled = (rtsr & RTSR_RDALE1) ? 1 : 0;
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alrm->pending = (rtsr & RTSR_RDAL1) ? 1 : 0;
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return 0;
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}
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static int pxa_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
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{
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struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
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u32 rtsr;
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spin_lock_irq(&pxa_rtc->lock);
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rtc_writel(pxa_rtc, RYAR1, ryxr_calc(&alrm->time));
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rtc_writel(pxa_rtc, RDAR1, rdxr_calc(&alrm->time));
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rtsr = rtc_readl(pxa_rtc, RTSR);
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if (alrm->enabled)
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rtsr |= RTSR_RDALE1;
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else
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rtsr &= ~RTSR_RDALE1;
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rtc_writel(pxa_rtc, RTSR, rtsr);
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spin_unlock_irq(&pxa_rtc->lock);
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return 0;
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}
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static int pxa_rtc_proc(struct device *dev, struct seq_file *seq)
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{
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struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
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seq_printf(seq, "trim/divider\t: 0x%08x\n", rtc_readl(pxa_rtc, RTTR));
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seq_printf(seq, "update_IRQ\t: %s\n",
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(rtc_readl(pxa_rtc, RTSR) & RTSR_HZE) ? "yes" : "no");
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seq_printf(seq, "periodic_IRQ\t: %s\n",
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(rtc_readl(pxa_rtc, RTSR) & RTSR_PIALE) ? "yes" : "no");
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seq_printf(seq, "periodic_freq\t: %u\n", rtc_readl(pxa_rtc, PIAR));
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return 0;
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}
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static const struct rtc_class_ops pxa_rtc_ops = {
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.open = pxa_rtc_open,
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.release = pxa_rtc_release,
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.read_time = pxa_rtc_read_time,
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.set_time = pxa_rtc_set_time,
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.read_alarm = pxa_rtc_read_alarm,
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.set_alarm = pxa_rtc_set_alarm,
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.alarm_irq_enable = pxa_alarm_irq_enable,
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.update_irq_enable = pxa_update_irq_enable,
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.proc = pxa_rtc_proc,
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.irq_set_state = pxa_periodic_irq_set_state,
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.irq_set_freq = pxa_periodic_irq_set_freq,
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};
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static int __init pxa_rtc_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct pxa_rtc *pxa_rtc;
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int ret;
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u32 rttr;
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pxa_rtc = kzalloc(sizeof(struct pxa_rtc), GFP_KERNEL);
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if (!pxa_rtc)
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return -ENOMEM;
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spin_lock_init(&pxa_rtc->lock);
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platform_set_drvdata(pdev, pxa_rtc);
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ret = -ENXIO;
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pxa_rtc->ress = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!pxa_rtc->ress) {
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dev_err(dev, "No I/O memory resource defined\n");
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goto err_ress;
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}
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pxa_rtc->irq_1Hz = platform_get_irq(pdev, 0);
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if (pxa_rtc->irq_1Hz < 0) {
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dev_err(dev, "No 1Hz IRQ resource defined\n");
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goto err_ress;
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}
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pxa_rtc->irq_Alrm = platform_get_irq(pdev, 1);
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if (pxa_rtc->irq_Alrm < 0) {
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dev_err(dev, "No alarm IRQ resource defined\n");
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goto err_ress;
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}
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ret = -ENOMEM;
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pxa_rtc->base = ioremap(pxa_rtc->ress->start,
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resource_size(pxa_rtc->ress));
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if (!pxa_rtc->base) {
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dev_err(&pdev->dev, "Unable to map pxa RTC I/O memory\n");
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goto err_map;
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}
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/*
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* If the clock divider is uninitialized then reset it to the
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* default value to get the 1Hz clock.
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*/
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if (rtc_readl(pxa_rtc, RTTR) == 0) {
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rttr = RTC_DEF_DIVIDER + (RTC_DEF_TRIM << 16);
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rtc_writel(pxa_rtc, RTTR, rttr);
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dev_warn(dev, "warning: initializing default clock"
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" divider/trim value\n");
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}
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rtsr_clear_bits(pxa_rtc, RTSR_PIALE | RTSR_RDALE1 | RTSR_HZE);
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pxa_rtc->rtc = rtc_device_register("pxa-rtc", &pdev->dev, &pxa_rtc_ops,
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THIS_MODULE);
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ret = PTR_ERR(pxa_rtc->rtc);
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if (IS_ERR(pxa_rtc->rtc)) {
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dev_err(dev, "Failed to register RTC device -> %d\n", ret);
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goto err_rtc_reg;
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}
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device_init_wakeup(dev, 1);
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return 0;
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err_rtc_reg:
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iounmap(pxa_rtc->base);
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err_ress:
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err_map:
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kfree(pxa_rtc);
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return ret;
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}
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static int __exit pxa_rtc_remove(struct platform_device *pdev)
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{
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struct pxa_rtc *pxa_rtc = platform_get_drvdata(pdev);
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rtc_device_unregister(pxa_rtc->rtc);
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spin_lock_irq(&pxa_rtc->lock);
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iounmap(pxa_rtc->base);
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spin_unlock_irq(&pxa_rtc->lock);
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kfree(pxa_rtc);
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return 0;
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}
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#ifdef CONFIG_PM
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static int pxa_rtc_suspend(struct device *dev)
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{
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struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
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if (device_may_wakeup(dev))
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enable_irq_wake(pxa_rtc->irq_Alrm);
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return 0;
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}
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static int pxa_rtc_resume(struct device *dev)
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{
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struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
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if (device_may_wakeup(dev))
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disable_irq_wake(pxa_rtc->irq_Alrm);
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return 0;
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}
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static const struct dev_pm_ops pxa_rtc_pm_ops = {
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.suspend = pxa_rtc_suspend,
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.resume = pxa_rtc_resume,
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};
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#endif
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static struct platform_driver pxa_rtc_driver = {
|
|
.remove = __exit_p(pxa_rtc_remove),
|
|
.driver = {
|
|
.name = "pxa-rtc",
|
|
#ifdef CONFIG_PM
|
|
.pm = &pxa_rtc_pm_ops,
|
|
#endif
|
|
},
|
|
};
|
|
|
|
static int __init pxa_rtc_init(void)
|
|
{
|
|
if (cpu_is_pxa27x() || cpu_is_pxa3xx())
|
|
return platform_driver_probe(&pxa_rtc_driver, pxa_rtc_probe);
|
|
|
|
return -ENODEV;
|
|
}
|
|
|
|
static void __exit pxa_rtc_exit(void)
|
|
{
|
|
platform_driver_unregister(&pxa_rtc_driver);
|
|
}
|
|
|
|
module_init(pxa_rtc_init);
|
|
module_exit(pxa_rtc_exit);
|
|
|
|
MODULE_AUTHOR("Robert Jarzmik <robert.jarzmik@free.fr>");
|
|
MODULE_DESCRIPTION("PXA27x/PXA3xx Realtime Clock Driver (RTC)");
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_ALIAS("platform:pxa-rtc");
|