413 lines
11 KiB
C
413 lines
11 KiB
C
/*
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* Copyright (C) 2003, Axis Communications AB.
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*/
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#include <asm/irq.h>
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#include <linux/irq.h>
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#include <linux/interrupt.h>
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#include <linux/smp.h>
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#include <linux/kernel.h>
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#include <linux/errno.h>
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#include <linux/init.h>
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#include <linux/profile.h>
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#include <linux/proc_fs.h>
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#include <linux/seq_file.h>
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#include <linux/threads.h>
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#include <linux/spinlock.h>
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#include <linux/kernel_stat.h>
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#include <asm/arch/hwregs/reg_map.h>
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#include <asm/arch/hwregs/reg_rdwr.h>
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#include <asm/arch/hwregs/intr_vect.h>
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#include <asm/arch/hwregs/intr_vect_defs.h>
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#define CPU_FIXED -1
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/* IRQ masks (refer to comment for crisv32_do_multiple) */
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#define TIMER_MASK (1 << (TIMER_INTR_VECT - FIRST_IRQ))
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#ifdef CONFIG_ETRAX_KGDB
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#if defined(CONFIG_ETRAX_KGDB_PORT0)
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#define IGNOREMASK (1 << (SER0_INTR_VECT - FIRST_IRQ))
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#elif defined(CONFIG_ETRAX_KGDB_PORT1)
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#define IGNOREMASK (1 << (SER1_INTR_VECT - FIRST_IRQ))
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#elif defined(CONFIG_ETRAX_KGB_PORT2)
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#define IGNOREMASK (1 << (SER2_INTR_VECT - FIRST_IRQ))
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#elif defined(CONFIG_ETRAX_KGDB_PORT3)
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#define IGNOREMASK (1 << (SER3_INTR_VECT - FIRST_IRQ))
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#endif
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#endif
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DEFINE_SPINLOCK(irq_lock);
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struct cris_irq_allocation
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{
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int cpu; /* The CPU to which the IRQ is currently allocated. */
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cpumask_t mask; /* The CPUs to which the IRQ may be allocated. */
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};
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struct cris_irq_allocation irq_allocations[NR_IRQS] =
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{[0 ... NR_IRQS - 1] = {0, CPU_MASK_ALL}};
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static unsigned long irq_regs[NR_CPUS] =
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{
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regi_irq,
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#ifdef CONFIG_SMP
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regi_irq2,
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#endif
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};
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unsigned long cpu_irq_counters[NR_CPUS];
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unsigned long irq_counters[NR_REAL_IRQS];
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/* From irq.c. */
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extern void weird_irq(void);
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/* From entry.S. */
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extern void system_call(void);
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extern void nmi_interrupt(void);
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extern void multiple_interrupt(void);
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extern void gdb_handle_exception(void);
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extern void i_mmu_refill(void);
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extern void i_mmu_invalid(void);
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extern void i_mmu_access(void);
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extern void i_mmu_execute(void);
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extern void d_mmu_refill(void);
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extern void d_mmu_invalid(void);
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extern void d_mmu_access(void);
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extern void d_mmu_write(void);
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/* From kgdb.c. */
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extern void kgdb_init(void);
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extern void breakpoint(void);
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/*
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* Build the IRQ handler stubs using macros from irq.h. First argument is the
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* IRQ number, the second argument is the corresponding bit in
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* intr_rw_vect_mask found in asm/arch/hwregs/intr_vect_defs.h.
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*/
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BUILD_IRQ(0x31, (1 << 0)) /* memarb */
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BUILD_IRQ(0x32, (1 << 1)) /* gen_io */
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BUILD_IRQ(0x33, (1 << 2)) /* iop0 */
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BUILD_IRQ(0x34, (1 << 3)) /* iop1 */
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BUILD_IRQ(0x35, (1 << 4)) /* iop2 */
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BUILD_IRQ(0x36, (1 << 5)) /* iop3 */
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BUILD_IRQ(0x37, (1 << 6)) /* dma0 */
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BUILD_IRQ(0x38, (1 << 7)) /* dma1 */
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BUILD_IRQ(0x39, (1 << 8)) /* dma2 */
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BUILD_IRQ(0x3a, (1 << 9)) /* dma3 */
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BUILD_IRQ(0x3b, (1 << 10)) /* dma4 */
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BUILD_IRQ(0x3c, (1 << 11)) /* dma5 */
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BUILD_IRQ(0x3d, (1 << 12)) /* dma6 */
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BUILD_IRQ(0x3e, (1 << 13)) /* dma7 */
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BUILD_IRQ(0x3f, (1 << 14)) /* dma8 */
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BUILD_IRQ(0x40, (1 << 15)) /* dma9 */
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BUILD_IRQ(0x41, (1 << 16)) /* ata */
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BUILD_IRQ(0x42, (1 << 17)) /* sser0 */
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BUILD_IRQ(0x43, (1 << 18)) /* sser1 */
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BUILD_IRQ(0x44, (1 << 19)) /* ser0 */
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BUILD_IRQ(0x45, (1 << 20)) /* ser1 */
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BUILD_IRQ(0x46, (1 << 21)) /* ser2 */
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BUILD_IRQ(0x47, (1 << 22)) /* ser3 */
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BUILD_IRQ(0x48, (1 << 23))
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BUILD_IRQ(0x49, (1 << 24)) /* eth0 */
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BUILD_IRQ(0x4a, (1 << 25)) /* eth1 */
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BUILD_TIMER_IRQ(0x4b, (1 << 26))/* timer */
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BUILD_IRQ(0x4c, (1 << 27)) /* bif_arb */
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BUILD_IRQ(0x4d, (1 << 28)) /* bif_dma */
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BUILD_IRQ(0x4e, (1 << 29)) /* ext */
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BUILD_IRQ(0x4f, (1 << 29)) /* ipi */
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/* Pointers to the low-level handlers. */
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static void (*interrupt[NR_IRQS])(void) = {
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IRQ0x31_interrupt, IRQ0x32_interrupt, IRQ0x33_interrupt,
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IRQ0x34_interrupt, IRQ0x35_interrupt, IRQ0x36_interrupt,
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IRQ0x37_interrupt, IRQ0x38_interrupt, IRQ0x39_interrupt,
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IRQ0x3a_interrupt, IRQ0x3b_interrupt, IRQ0x3c_interrupt,
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IRQ0x3d_interrupt, IRQ0x3e_interrupt, IRQ0x3f_interrupt,
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IRQ0x40_interrupt, IRQ0x41_interrupt, IRQ0x42_interrupt,
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IRQ0x43_interrupt, IRQ0x44_interrupt, IRQ0x45_interrupt,
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IRQ0x46_interrupt, IRQ0x47_interrupt, IRQ0x48_interrupt,
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IRQ0x49_interrupt, IRQ0x4a_interrupt, IRQ0x4b_interrupt,
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IRQ0x4c_interrupt, IRQ0x4d_interrupt, IRQ0x4e_interrupt,
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IRQ0x4f_interrupt
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};
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void
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block_irq(int irq, int cpu)
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{
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int intr_mask;
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unsigned long flags;
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spin_lock_irqsave(&irq_lock, flags);
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intr_mask = REG_RD_INT(intr_vect, irq_regs[cpu], rw_mask);
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/* Remember; 1 let through, 0 block. */
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intr_mask &= ~(1 << (irq - FIRST_IRQ));
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REG_WR_INT(intr_vect, irq_regs[cpu], rw_mask, intr_mask);
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spin_unlock_irqrestore(&irq_lock, flags);
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}
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void
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unblock_irq(int irq, int cpu)
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{
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int intr_mask;
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unsigned long flags;
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spin_lock_irqsave(&irq_lock, flags);
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intr_mask = REG_RD_INT(intr_vect, irq_regs[cpu], rw_mask);
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/* Remember; 1 let through, 0 block. */
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intr_mask |= (1 << (irq - FIRST_IRQ));
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REG_WR_INT(intr_vect, irq_regs[cpu], rw_mask, intr_mask);
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spin_unlock_irqrestore(&irq_lock, flags);
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}
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/* Find out which CPU the irq should be allocated to. */
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static int irq_cpu(int irq)
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{
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int cpu;
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unsigned long flags;
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spin_lock_irqsave(&irq_lock, flags);
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cpu = irq_allocations[irq - FIRST_IRQ].cpu;
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/* Fixed interrupts stay on the local CPU. */
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if (cpu == CPU_FIXED)
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{
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spin_unlock_irqrestore(&irq_lock, flags);
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return smp_processor_id();
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}
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/* Let the interrupt stay if possible */
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if (cpu_isset(cpu, irq_allocations[irq - FIRST_IRQ].mask))
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goto out;
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/* IRQ must be moved to another CPU. */
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cpu = first_cpu(irq_allocations[irq - FIRST_IRQ].mask);
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irq_allocations[irq - FIRST_IRQ].cpu = cpu;
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out:
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spin_unlock_irqrestore(&irq_lock, flags);
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return cpu;
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}
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void
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mask_irq(int irq)
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{
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int cpu;
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for (cpu = 0; cpu < NR_CPUS; cpu++)
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block_irq(irq, cpu);
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}
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void
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unmask_irq(int irq)
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{
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unblock_irq(irq, irq_cpu(irq));
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}
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static unsigned int startup_crisv32_irq(unsigned int irq)
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{
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unmask_irq(irq);
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return 0;
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}
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static void shutdown_crisv32_irq(unsigned int irq)
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{
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mask_irq(irq);
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}
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static void enable_crisv32_irq(unsigned int irq)
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{
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unmask_irq(irq);
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}
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static void disable_crisv32_irq(unsigned int irq)
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{
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mask_irq(irq);
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}
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static void ack_crisv32_irq(unsigned int irq)
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{
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}
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static void end_crisv32_irq(unsigned int irq)
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{
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}
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void set_affinity_crisv32_irq(unsigned int irq, cpumask_t dest)
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{
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unsigned long flags;
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spin_lock_irqsave(&irq_lock, flags);
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irq_allocations[irq - FIRST_IRQ].mask = dest;
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spin_unlock_irqrestore(&irq_lock, flags);
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}
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static struct hw_interrupt_type crisv32_irq_type = {
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.typename = "CRISv32",
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.startup = startup_crisv32_irq,
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.shutdown = shutdown_crisv32_irq,
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.enable = enable_crisv32_irq,
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.disable = disable_crisv32_irq,
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.ack = ack_crisv32_irq,
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.end = end_crisv32_irq,
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.set_affinity = set_affinity_crisv32_irq
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};
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void
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set_exception_vector(int n, irqvectptr addr)
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{
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etrax_irv->v[n] = (irqvectptr) addr;
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}
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extern void do_IRQ(int irq, struct pt_regs * regs);
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void
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crisv32_do_IRQ(int irq, int block, struct pt_regs* regs)
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{
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/* Interrupts that may not be moved to another CPU and
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* are IRQF_DISABLED may skip blocking. This is currently
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* only valid for the timer IRQ and the IPI and is used
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* for the timer interrupt to avoid watchdog starvation.
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*/
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if (!block) {
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do_IRQ(irq, regs);
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return;
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}
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block_irq(irq, smp_processor_id());
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do_IRQ(irq, regs);
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unblock_irq(irq, irq_cpu(irq));
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}
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/* If multiple interrupts occur simultaneously we get a multiple
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* interrupt from the CPU and software has to sort out which
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* interrupts that happened. There are two special cases here:
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*
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* 1. Timer interrupts may never be blocked because of the
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* watchdog (refer to comment in include/asr/arch/irq.h)
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* 2. GDB serial port IRQs are unhandled here and will be handled
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* as a single IRQ when it strikes again because the GDB
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* stubb wants to save the registers in its own fashion.
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*/
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void
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crisv32_do_multiple(struct pt_regs* regs)
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{
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int cpu;
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int mask;
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int masked;
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int bit;
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cpu = smp_processor_id();
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/* An extra irq_enter here to prevent softIRQs to run after
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* each do_IRQ. This will decrease the interrupt latency.
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*/
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irq_enter();
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/* Get which IRQs that happened. */
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masked = REG_RD_INT(intr_vect, irq_regs[cpu], r_masked_vect);
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/* Calculate new IRQ mask with these IRQs disabled. */
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mask = REG_RD_INT(intr_vect, irq_regs[cpu], rw_mask);
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mask &= ~masked;
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/* Timer IRQ is never masked */
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if (masked & TIMER_MASK)
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mask |= TIMER_MASK;
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/* Block all the IRQs */
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REG_WR_INT(intr_vect, irq_regs[cpu], rw_mask, mask);
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/* Check for timer IRQ and handle it special. */
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if (masked & TIMER_MASK) {
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masked &= ~TIMER_MASK;
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do_IRQ(TIMER_INTR_VECT, regs);
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}
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#ifdef IGNORE_MASK
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/* Remove IRQs that can't be handled as multiple. */
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masked &= ~IGNORE_MASK;
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#endif
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/* Handle the rest of the IRQs. */
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for (bit = 0; bit < 32; bit++)
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{
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if (masked & (1 << bit))
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do_IRQ(bit + FIRST_IRQ, regs);
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}
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/* Unblock all the IRQs. */
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mask = REG_RD_INT(intr_vect, irq_regs[cpu], rw_mask);
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mask |= masked;
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REG_WR_INT(intr_vect, irq_regs[cpu], rw_mask, mask);
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/* This irq_exit() will trigger the soft IRQs. */
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irq_exit();
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}
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/*
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* This is called by start_kernel. It fixes the IRQ masks and setup the
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* interrupt vector table to point to bad_interrupt pointers.
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*/
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void __init
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init_IRQ(void)
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{
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int i;
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int j;
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reg_intr_vect_rw_mask vect_mask = {0};
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/* Clear all interrupts masks. */
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REG_WR(intr_vect, regi_irq, rw_mask, vect_mask);
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for (i = 0; i < 256; i++)
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etrax_irv->v[i] = weird_irq;
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/* Point all IRQs to bad handlers. */
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for (i = FIRST_IRQ, j = 0; j < NR_IRQS; i++, j++) {
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irq_desc[j].chip = &crisv32_irq_type;
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set_exception_vector(i, interrupt[j]);
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}
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/* Mark Timer and IPI IRQs as CPU local */
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irq_allocations[TIMER_INTR_VECT - FIRST_IRQ].cpu = CPU_FIXED;
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irq_desc[TIMER_INTR_VECT].status |= IRQ_PER_CPU;
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irq_allocations[IPI_INTR_VECT - FIRST_IRQ].cpu = CPU_FIXED;
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irq_desc[IPI_INTR_VECT].status |= IRQ_PER_CPU;
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set_exception_vector(0x00, nmi_interrupt);
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set_exception_vector(0x30, multiple_interrupt);
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/* Set up handler for various MMU bus faults. */
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set_exception_vector(0x04, i_mmu_refill);
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set_exception_vector(0x05, i_mmu_invalid);
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set_exception_vector(0x06, i_mmu_access);
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set_exception_vector(0x07, i_mmu_execute);
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set_exception_vector(0x08, d_mmu_refill);
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set_exception_vector(0x09, d_mmu_invalid);
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set_exception_vector(0x0a, d_mmu_access);
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set_exception_vector(0x0b, d_mmu_write);
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/* The system-call trap is reached by "break 13". */
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set_exception_vector(0x1d, system_call);
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/* Exception handlers for debugging, both user-mode and kernel-mode. */
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/* Break 8. */
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set_exception_vector(0x18, gdb_handle_exception);
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/* Hardware single step. */
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set_exception_vector(0x3, gdb_handle_exception);
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/* Hardware breakpoint. */
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set_exception_vector(0xc, gdb_handle_exception);
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#ifdef CONFIG_ETRAX_KGDB
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kgdb_init();
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/* Everything is set up; now trap the kernel. */
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breakpoint();
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#endif
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}
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