388 lines
9.5 KiB
C
388 lines
9.5 KiB
C
/*arch/ppc/platforms/mpc885ads-setup.c
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*
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* Platform setup for the Freescale mpc885ads board
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*
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* Vitaly Bordug <vbordug@ru.mvista.com>
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*
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* Copyright 2005 MontaVista Software Inc.
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*
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* This file is licensed under the terms of the GNU General Public License
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* version 2. This program is licensed "as is" without any warranty of any
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* kind, whether express or implied.
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/param.h>
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#include <linux/string.h>
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#include <linux/ioport.h>
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#include <linux/device.h>
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#include <linux/delay.h>
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#include <linux/root_dev.h>
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#include <linux/fs_enet_pd.h>
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#include <linux/fs_uart_pd.h>
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#include <linux/mii.h>
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#include <asm/delay.h>
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#include <asm/io.h>
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#include <asm/machdep.h>
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#include <asm/page.h>
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#include <asm/processor.h>
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#include <asm/system.h>
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#include <asm/time.h>
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#include <asm/ppcboot.h>
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#include <asm/mpc8xx.h>
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#include <asm/8xx_immap.h>
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#include <asm/commproc.h>
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#include <asm/fs_pd.h>
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#include <asm/prom.h>
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extern void cpm_reset(void);
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extern void mpc8xx_show_cpuinfo(struct seq_file*);
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extern void mpc8xx_restart(char *cmd);
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extern void mpc8xx_calibrate_decr(void);
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extern int mpc8xx_set_rtc_time(struct rtc_time *tm);
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extern void mpc8xx_get_rtc_time(struct rtc_time *tm);
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extern void m8xx_pic_init(void);
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extern unsigned int mpc8xx_get_irq(void);
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static void init_smc1_uart_ioports(struct fs_uart_platform_info* fpi);
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static void init_smc2_uart_ioports(struct fs_uart_platform_info* fpi);
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static void init_scc3_ioports(struct fs_platform_info* ptr);
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void __init mpc885ads_board_setup(void)
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{
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cpm8xx_t *cp;
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unsigned int *bcsr_io;
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u8 tmpval8;
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#ifdef CONFIG_FS_ENET
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iop8xx_t *io_port;
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#endif
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bcsr_io = ioremap(BCSR1, sizeof(unsigned long));
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cp = (cpm8xx_t *)immr_map(im_cpm);
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if (bcsr_io == NULL) {
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printk(KERN_CRIT "Could not remap BCSR\n");
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return;
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}
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#ifdef CONFIG_SERIAL_CPM_SMC1
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clrbits32(bcsr_io, BCSR1_RS232EN_1);
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clrbits32(&cp->cp_simode, 0xe0000000 >> 17); /* brg1 */
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tmpval8 = in_8(&(cp->cp_smc[0].smc_smcm)) | (SMCM_RX | SMCM_TX);
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out_8(&(cp->cp_smc[0].smc_smcm), tmpval8);
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clrbits16(&cp->cp_smc[0].smc_smcmr, SMCMR_REN | SMCMR_TEN); /* brg1 */
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#else
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setbits32(bcsr_io,BCSR1_RS232EN_1);
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out_be16(&cp->cp_smc[0].smc_smcmr, 0);
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out_8(&cp->cp_smc[0].smc_smce, 0);
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#endif
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#ifdef CONFIG_SERIAL_CPM_SMC2
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clrbits32(bcsr_io,BCSR1_RS232EN_2);
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clrbits32(&cp->cp_simode, 0xe0000000 >> 1);
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setbits32(&cp->cp_simode, 0x20000000 >> 1); /* brg2 */
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tmpval8 = in_8(&(cp->cp_smc[1].smc_smcm)) | (SMCM_RX | SMCM_TX);
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out_8(&(cp->cp_smc[1].smc_smcm), tmpval8);
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clrbits16(&cp->cp_smc[1].smc_smcmr, SMCMR_REN | SMCMR_TEN);
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init_smc2_uart_ioports(0);
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#else
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setbits32(bcsr_io,BCSR1_RS232EN_2);
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out_be16(&cp->cp_smc[1].smc_smcmr, 0);
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out_8(&cp->cp_smc[1].smc_smce, 0);
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#endif
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immr_unmap(cp);
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iounmap(bcsr_io);
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#ifdef CONFIG_FS_ENET
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/* use MDC for MII (common) */
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io_port = (iop8xx_t*)immr_map(im_ioport);
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setbits16(&io_port->iop_pdpar, 0x0080);
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clrbits16(&io_port->iop_pddir, 0x0080);
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bcsr_io = ioremap(BCSR5, sizeof(unsigned long));
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clrbits32(bcsr_io,BCSR5_MII1_EN);
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clrbits32(bcsr_io,BCSR5_MII1_RST);
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#ifndef CONFIG_FC_ENET_HAS_SCC
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clrbits32(bcsr_io,BCSR5_MII2_EN);
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clrbits32(bcsr_io,BCSR5_MII2_RST);
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#endif
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iounmap(bcsr_io);
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immr_unmap(io_port);
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#endif
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}
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static void init_fec1_ioports(struct fs_platform_info* ptr)
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{
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cpm8xx_t *cp = (cpm8xx_t *)immr_map(im_cpm);
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iop8xx_t *io_port = (iop8xx_t *)immr_map(im_ioport);
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/* configure FEC1 pins */
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setbits16(&io_port->iop_papar, 0xf830);
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setbits16(&io_port->iop_padir, 0x0830);
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clrbits16(&io_port->iop_padir, 0xf000);
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setbits32(&cp->cp_pbpar, 0x00001001);
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clrbits32(&cp->cp_pbdir, 0x00001001);
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setbits16(&io_port->iop_pcpar, 0x000c);
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clrbits16(&io_port->iop_pcdir, 0x000c);
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setbits32(&cp->cp_pepar, 0x00000003);
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setbits32(&cp->cp_pedir, 0x00000003);
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clrbits32(&cp->cp_peso, 0x00000003);
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clrbits32(&cp->cp_cptr, 0x00000100);
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immr_unmap(io_port);
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immr_unmap(cp);
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}
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static void init_fec2_ioports(struct fs_platform_info* ptr)
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{
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cpm8xx_t *cp = (cpm8xx_t *)immr_map(im_cpm);
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iop8xx_t *io_port = (iop8xx_t *)immr_map(im_ioport);
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/* configure FEC2 pins */
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setbits32(&cp->cp_pepar, 0x0003fffc);
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setbits32(&cp->cp_pedir, 0x0003fffc);
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clrbits32(&cp->cp_peso, 0x000087fc);
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setbits32(&cp->cp_peso, 0x00037800);
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clrbits32(&cp->cp_cptr, 0x00000080);
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immr_unmap(io_port);
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immr_unmap(cp);
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}
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void init_fec_ioports(struct fs_platform_info *fpi)
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{
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int fec_no = fs_get_fec_index(fpi->fs_no);
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switch (fec_no) {
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case 0:
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init_fec1_ioports(fpi);
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break;
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case 1:
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init_fec2_ioports(fpi);
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break;
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default:
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printk(KERN_ERR "init_fec_ioports: invalid FEC number\n");
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return;
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}
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}
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static void init_scc3_ioports(struct fs_platform_info* fpi)
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{
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unsigned *bcsr_io;
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iop8xx_t *io_port;
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cpm8xx_t *cp;
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bcsr_io = ioremap(BCSR_ADDR, BCSR_SIZE);
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io_port = (iop8xx_t *)immr_map(im_ioport);
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cp = (cpm8xx_t *)immr_map(im_cpm);
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if (bcsr_io == NULL) {
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printk(KERN_CRIT "Could not remap BCSR\n");
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return;
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}
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/* Enable the PHY.
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*/
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clrbits32(bcsr_io+4, BCSR4_ETH10_RST);
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udelay(1000);
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setbits32(bcsr_io+4, BCSR4_ETH10_RST);
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/* Configure port A pins for Txd and Rxd.
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*/
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setbits16(&io_port->iop_papar, PA_ENET_RXD | PA_ENET_TXD);
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clrbits16(&io_port->iop_padir, PA_ENET_RXD | PA_ENET_TXD);
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/* Configure port C pins to enable CLSN and RENA.
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*/
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clrbits16(&io_port->iop_pcpar, PC_ENET_CLSN | PC_ENET_RENA);
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clrbits16(&io_port->iop_pcdir, PC_ENET_CLSN | PC_ENET_RENA);
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setbits16(&io_port->iop_pcso, PC_ENET_CLSN | PC_ENET_RENA);
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/* Configure port E for TCLK and RCLK.
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*/
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setbits32(&cp->cp_pepar, PE_ENET_TCLK | PE_ENET_RCLK);
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clrbits32(&cp->cp_pepar, PE_ENET_TENA);
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clrbits32(&cp->cp_pedir,
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PE_ENET_TCLK | PE_ENET_RCLK | PE_ENET_TENA);
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clrbits32(&cp->cp_peso, PE_ENET_TCLK | PE_ENET_RCLK);
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setbits32(&cp->cp_peso, PE_ENET_TENA);
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/* Configure Serial Interface clock routing.
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* First, clear all SCC bits to zero, then set the ones we want.
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*/
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clrbits32(&cp->cp_sicr, SICR_ENET_MASK);
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setbits32(&cp->cp_sicr, SICR_ENET_CLKRT);
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/* Disable Rx and Tx. SMC1 sshould be stopped if SCC3 eternet are used.
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*/
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clrbits16(&cp->cp_smc[0].smc_smcmr, SMCMR_REN | SMCMR_TEN);
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/* On the MPC885ADS SCC ethernet PHY is initialized in the full duplex mode
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* by H/W setting after reset. SCC ethernet controller support only half duplex.
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* This discrepancy of modes causes a lot of carrier lost errors.
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*/
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/* In the original SCC enet driver the following code is placed at
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the end of the initialization */
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setbits32(&cp->cp_pepar, PE_ENET_TENA);
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clrbits32(&cp->cp_pedir, PE_ENET_TENA);
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setbits32(&cp->cp_peso, PE_ENET_TENA);
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setbits32(bcsr_io+4, BCSR1_ETHEN);
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iounmap(bcsr_io);
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immr_unmap(io_port);
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immr_unmap(cp);
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}
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void init_scc_ioports(struct fs_platform_info *fpi)
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{
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int scc_no = fs_get_scc_index(fpi->fs_no);
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switch (scc_no) {
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case 2:
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init_scc3_ioports(fpi);
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break;
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default:
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printk(KERN_ERR "init_scc_ioports: invalid SCC number\n");
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return;
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}
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}
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static void init_smc1_uart_ioports(struct fs_uart_platform_info* ptr)
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{
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unsigned *bcsr_io;
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cpm8xx_t *cp;
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cp = (cpm8xx_t *)immr_map(im_cpm);
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setbits32(&cp->cp_pepar, 0x000000c0);
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clrbits32(&cp->cp_pedir, 0x000000c0);
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clrbits32(&cp->cp_peso, 0x00000040);
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setbits32(&cp->cp_peso, 0x00000080);
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immr_unmap(cp);
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bcsr_io = ioremap(BCSR1, sizeof(unsigned long));
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if (bcsr_io == NULL) {
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printk(KERN_CRIT "Could not remap BCSR1\n");
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return;
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}
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clrbits32(bcsr_io,BCSR1_RS232EN_1);
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iounmap(bcsr_io);
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}
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static void init_smc2_uart_ioports(struct fs_uart_platform_info* fpi)
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{
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unsigned *bcsr_io;
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cpm8xx_t *cp;
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cp = (cpm8xx_t *)immr_map(im_cpm);
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setbits32(&cp->cp_pepar, 0x00000c00);
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clrbits32(&cp->cp_pedir, 0x00000c00);
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clrbits32(&cp->cp_peso, 0x00000400);
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setbits32(&cp->cp_peso, 0x00000800);
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immr_unmap(cp);
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bcsr_io = ioremap(BCSR1, sizeof(unsigned long));
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if (bcsr_io == NULL) {
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printk(KERN_CRIT "Could not remap BCSR1\n");
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return;
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}
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clrbits32(bcsr_io,BCSR1_RS232EN_2);
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iounmap(bcsr_io);
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}
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void init_smc_ioports(struct fs_uart_platform_info *data)
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{
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int smc_no = fs_uart_id_fsid2smc(data->fs_no);
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switch (smc_no) {
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case 0:
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init_smc1_uart_ioports(data);
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data->brg = data->clk_rx;
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break;
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case 1:
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init_smc2_uart_ioports(data);
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data->brg = data->clk_rx;
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break;
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default:
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printk(KERN_ERR "init_scc_ioports: invalid SCC number\n");
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return;
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}
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}
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int platform_device_skip(char *model, int id)
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{
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#ifdef CONFIG_MPC8xx_SECOND_ETH_SCC3
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const char *dev = "FEC";
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int n = 2;
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#else
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const char *dev = "SCC";
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int n = 3;
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#endif
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if (!strcmp(model, dev) && n == id)
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return 1;
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return 0;
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}
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static void __init mpc885ads_setup_arch(void)
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{
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struct device_node *cpu;
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cpu = of_find_node_by_type(NULL, "cpu");
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if (cpu != 0) {
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const unsigned int *fp;
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fp = get_property(cpu, "clock-frequency", NULL);
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if (fp != 0)
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loops_per_jiffy = *fp / HZ;
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else
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loops_per_jiffy = 50000000 / HZ;
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of_node_put(cpu);
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}
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cpm_reset();
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mpc885ads_board_setup();
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ROOT_DEV = Root_NFS;
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}
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static int __init mpc885ads_probe(void)
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{
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char *model = of_get_flat_dt_prop(of_get_flat_dt_root(),
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"model", NULL);
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if (model == NULL)
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return 0;
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if (strcmp(model, "MPC885ADS"))
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return 0;
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return 1;
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}
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define_machine(mpc885_ads) {
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.name = "MPC885 ADS",
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.probe = mpc885ads_probe,
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.setup_arch = mpc885ads_setup_arch,
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.init_IRQ = m8xx_pic_init,
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.show_cpuinfo = mpc8xx_show_cpuinfo,
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.get_irq = mpc8xx_get_irq,
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.restart = mpc8xx_restart,
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.calibrate_decr = mpc8xx_calibrate_decr,
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.set_rtc_time = mpc8xx_set_rtc_time,
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.get_rtc_time = mpc8xx_get_rtc_time,
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};
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