98 lines
2.7 KiB
C
98 lines
2.7 KiB
C
/*
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* arch/ppc/platforms/ocotea.h
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*
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* Ocotea board definitions
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*
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* Matt Porter <mporter@kernel.crashing.org>
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*
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* Copyright 2003-2005 MontaVista Software Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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*/
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#ifdef __KERNEL__
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#ifndef __ASM_OCOTEA_H__
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#define __ASM_OCOTEA_H__
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#include <linux/config.h>
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#include <platforms/4xx/ibm440gx.h>
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/* F/W TLB mapping used in bootloader glue to reset EMAC */
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#define PPC44x_EMAC0_MR0 0xe0000800
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/* Location of MAC addresses in PIBS image */
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#define PIBS_FLASH_BASE 0xfff00000
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#define PIBS_MAC_BASE (PIBS_FLASH_BASE+0xb0500)
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#define PIBS_MAC_SIZE 0x200
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#define PIBS_MAC_OFFSET 0x100
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/* External timer clock frequency */
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#define OCOTEA_TMR_CLK 25000000
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/* RTC/NVRAM location */
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#define OCOTEA_RTC_ADDR 0x0000000148000000ULL
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#define OCOTEA_RTC_SIZE 0x2000
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/* Flash */
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#define OCOTEA_FPGA_REG_0 0x0000000148300000ULL
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#define OCOTEA_BOOT_LARGE_FLASH(x) (x & 0x40)
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#define OCOTEA_SMALL_FLASH_LOW 0x00000001ff900000ULL
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#define OCOTEA_SMALL_FLASH_HIGH 0x00000001fff00000ULL
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#define OCOTEA_SMALL_FLASH_SIZE 0x100000
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#define OCOTEA_LARGE_FLASH_LOW 0x00000001ff800000ULL
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#define OCOTEA_LARGE_FLASH_HIGH 0x00000001ffc00000ULL
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#define OCOTEA_LARGE_FLASH_SIZE 0x400000
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/* FPGA_REG_3 (Ethernet Groups) */
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#define OCOTEA_FPGA_REG_3 0x0000000148300003ULL
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/*
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* Serial port defines
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*/
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#define RS_TABLE_SIZE 2
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#if defined(__BOOTER__)
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/* OpenBIOS defined UART mappings, used by bootloader shim */
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#define UART0_IO_BASE 0xE0000200
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#define UART1_IO_BASE 0xE0000300
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#else
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/* head_44x.S created UART mapping, used before early_serial_setup.
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* We cannot use default OpenBIOS UART mappings because they
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* don't work for configurations with more than 512M RAM. --ebs
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*/
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#define UART0_IO_BASE 0xF0000200
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#define UART1_IO_BASE 0xF0000300
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#endif
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#define BASE_BAUD 11059200/16
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#define STD_UART_OP(num) \
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{ 0, BASE_BAUD, 0, UART##num##_INT, \
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(ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST), \
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iomem_base: (void*)UART##num##_IO_BASE, \
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io_type: SERIAL_IO_MEM},
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#define SERIAL_PORT_DFNS \
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STD_UART_OP(0) \
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STD_UART_OP(1)
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/* PCI support */
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#define OCOTEA_PCI_LOWER_IO 0x00000000
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#define OCOTEA_PCI_UPPER_IO 0x0000ffff
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#define OCOTEA_PCI_LOWER_MEM 0x80000000
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#define OCOTEA_PCI_UPPER_MEM 0xffffefff
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#define OCOTEA_PCI_CFGREGS_BASE 0x000000020ec00000ULL
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#define OCOTEA_PCI_CFGA_PLB32 0x0ec00000
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#define OCOTEA_PCI_CFGD_PLB32 0x0ec00004
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#define OCOTEA_PCI_IO_BASE 0x0000000208000000ULL
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#define OCOTEA_PCI_IO_SIZE 0x00010000
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#define OCOTEA_PCI_MEM_OFFSET 0x00000000
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#endif /* __ASM_OCOTEA_H__ */
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#endif /* __KERNEL__ */
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