421 lines
13 KiB
C
421 lines
13 KiB
C
/*
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* arch/sh/boards/superh/microdev/setup.c
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*
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* Copyright (C) 2003 Sean McGoogan (Sean.McGoogan@superh.com)
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* Copyright (C) 2003, 2004 SuperH, Inc.
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* Copyright (C) 2004, 2005 Paul Mundt
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*
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* SuperH SH4-202 MicroDev board support.
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*
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* May be copied or modified under the terms of the GNU General Public
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* License. See linux/COPYING for more information.
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*/
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#include <linux/config.h>
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <linux/ioport.h>
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#include <video/s1d13xxxfb.h>
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#include <asm/microdev.h>
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#include <asm/io.h>
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#include <asm/machvec.h>
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extern void microdev_heartbeat(void);
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/*
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* The Machine Vector
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*/
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struct sh_machine_vector mv_sh4202_microdev __initmv = {
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.mv_nr_irqs = 72, /* QQQ need to check this - use the MACRO */
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.mv_inb = microdev_inb,
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.mv_inw = microdev_inw,
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.mv_inl = microdev_inl,
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.mv_outb = microdev_outb,
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.mv_outw = microdev_outw,
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.mv_outl = microdev_outl,
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.mv_inb_p = microdev_inb_p,
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.mv_inw_p = microdev_inw_p,
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.mv_inl_p = microdev_inl_p,
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.mv_outb_p = microdev_outb_p,
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.mv_outw_p = microdev_outw_p,
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.mv_outl_p = microdev_outl_p,
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.mv_insb = microdev_insb,
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.mv_insw = microdev_insw,
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.mv_insl = microdev_insl,
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.mv_outsb = microdev_outsb,
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.mv_outsw = microdev_outsw,
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.mv_outsl = microdev_outsl,
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.mv_init_irq = init_microdev_irq,
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#ifdef CONFIG_HEARTBEAT
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.mv_heartbeat = microdev_heartbeat,
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#endif
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};
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ALIAS_MV(sh4202_microdev)
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/****************************************************************************/
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/*
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* Setup for the SMSC FDC37C93xAPM
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*/
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#define SMSC_CONFIG_PORT_ADDR (0x3F0)
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#define SMSC_INDEX_PORT_ADDR SMSC_CONFIG_PORT_ADDR
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#define SMSC_DATA_PORT_ADDR (SMSC_INDEX_PORT_ADDR + 1)
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#define SMSC_ENTER_CONFIG_KEY 0x55
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#define SMSC_EXIT_CONFIG_KEY 0xaa
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#define SMCS_LOGICAL_DEV_INDEX 0x07 /* Logical Device Number */
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#define SMSC_DEVICE_ID_INDEX 0x20 /* Device ID */
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#define SMSC_DEVICE_REV_INDEX 0x21 /* Device Revision */
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#define SMSC_ACTIVATE_INDEX 0x30 /* Activate */
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#define SMSC_PRIMARY_BASE_INDEX 0x60 /* Primary Base Address */
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#define SMSC_SECONDARY_BASE_INDEX 0x62 /* Secondary Base Address */
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#define SMSC_PRIMARY_INT_INDEX 0x70 /* Primary Interrupt Select */
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#define SMSC_SECONDARY_INT_INDEX 0x72 /* Secondary Interrupt Select */
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#define SMSC_HDCS0_INDEX 0xf0 /* HDCS0 Address Decoder */
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#define SMSC_HDCS1_INDEX 0xf1 /* HDCS1 Address Decoder */
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#define SMSC_IDE1_DEVICE 1 /* IDE #1 logical device */
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#define SMSC_IDE2_DEVICE 2 /* IDE #2 logical device */
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#define SMSC_PARALLEL_DEVICE 3 /* Parallel Port logical device */
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#define SMSC_SERIAL1_DEVICE 4 /* Serial #1 logical device */
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#define SMSC_SERIAL2_DEVICE 5 /* Serial #2 logical device */
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#define SMSC_KEYBOARD_DEVICE 7 /* Keyboard logical device */
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#define SMSC_CONFIG_REGISTERS 8 /* Configuration Registers (Aux I/O) */
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#define SMSC_READ_INDEXED(index) ({ \
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outb((index), SMSC_INDEX_PORT_ADDR); \
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inb(SMSC_DATA_PORT_ADDR); })
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#define SMSC_WRITE_INDEXED(val, index) ({ \
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outb((index), SMSC_INDEX_PORT_ADDR); \
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outb((val), SMSC_DATA_PORT_ADDR); })
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#define IDE1_PRIMARY_BASE 0x01f0 /* Task File Registe base for IDE #1 */
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#define IDE1_SECONDARY_BASE 0x03f6 /* Miscellaneous AT registers for IDE #1 */
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#define IDE2_PRIMARY_BASE 0x0170 /* Task File Registe base for IDE #2 */
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#define IDE2_SECONDARY_BASE 0x0376 /* Miscellaneous AT registers for IDE #2 */
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#define SERIAL1_PRIMARY_BASE 0x03f8
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#define SERIAL2_PRIMARY_BASE 0x02f8
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#define MSB(x) ( (x) >> 8 )
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#define LSB(x) ( (x) & 0xff )
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/* General-Purpose base address on CPU-board FPGA */
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#define MICRODEV_FPGA_GP_BASE 0xa6100000ul
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/* assume a Keyboard Controller is present */
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int microdev_kbd_controller_present = 1;
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const char *get_system_type(void)
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{
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return "SH4-202 MicroDev";
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}
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static struct resource smc91x_resources[] = {
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[0] = {
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.start = 0x300,
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.end = 0x300 + 0x0001000 - 1,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = MICRODEV_LINUX_IRQ_ETHERNET,
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.end = MICRODEV_LINUX_IRQ_ETHERNET,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device smc91x_device = {
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.name = "smc91x",
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.id = -1,
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.num_resources = ARRAY_SIZE(smc91x_resources),
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.resource = smc91x_resources,
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};
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#ifdef CONFIG_FB_S1D13XXX
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static struct s1d13xxxfb_regval s1d13806_initregs[] = {
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{ S1DREG_MISC, 0x00 },
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{ S1DREG_COM_DISP_MODE, 0x00 },
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{ S1DREG_GPIO_CNF0, 0x00 },
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{ S1DREG_GPIO_CNF1, 0x00 },
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{ S1DREG_GPIO_CTL0, 0x00 },
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{ S1DREG_GPIO_CTL1, 0x00 },
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{ S1DREG_CLK_CNF, 0x02 },
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{ S1DREG_LCD_CLK_CNF, 0x01 },
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{ S1DREG_CRT_CLK_CNF, 0x03 },
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{ S1DREG_MPLUG_CLK_CNF, 0x03 },
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{ S1DREG_CPU2MEM_WST_SEL, 0x02 },
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{ S1DREG_SDRAM_REF_RATE, 0x03 },
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{ S1DREG_SDRAM_TC0, 0x00 },
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{ S1DREG_SDRAM_TC1, 0x01 },
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{ S1DREG_MEM_CNF, 0x80 },
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{ S1DREG_PANEL_TYPE, 0x25 },
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{ S1DREG_MOD_RATE, 0x00 },
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{ S1DREG_LCD_DISP_HWIDTH, 0x63 },
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{ S1DREG_LCD_NDISP_HPER, 0x1e },
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{ S1DREG_TFT_FPLINE_START, 0x06 },
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{ S1DREG_TFT_FPLINE_PWIDTH, 0x03 },
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{ S1DREG_LCD_DISP_VHEIGHT0, 0x57 },
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{ S1DREG_LCD_DISP_VHEIGHT1, 0x02 },
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{ S1DREG_LCD_NDISP_VPER, 0x00 },
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{ S1DREG_TFT_FPFRAME_START, 0x0a },
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{ S1DREG_TFT_FPFRAME_PWIDTH, 0x81 },
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{ S1DREG_LCD_DISP_MODE, 0x03 },
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{ S1DREG_LCD_MISC, 0x00 },
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{ S1DREG_LCD_DISP_START0, 0x00 },
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{ S1DREG_LCD_DISP_START1, 0x00 },
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{ S1DREG_LCD_DISP_START2, 0x00 },
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{ S1DREG_LCD_MEM_OFF0, 0x90 },
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{ S1DREG_LCD_MEM_OFF1, 0x01 },
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{ S1DREG_LCD_PIX_PAN, 0x00 },
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{ S1DREG_LCD_DISP_FIFO_HTC, 0x00 },
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{ S1DREG_LCD_DISP_FIFO_LTC, 0x00 },
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{ S1DREG_CRT_DISP_HWIDTH, 0x63 },
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{ S1DREG_CRT_NDISP_HPER, 0x1f },
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{ S1DREG_CRT_HRTC_START, 0x04 },
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{ S1DREG_CRT_HRTC_PWIDTH, 0x8f },
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{ S1DREG_CRT_DISP_VHEIGHT0, 0x57 },
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{ S1DREG_CRT_DISP_VHEIGHT1, 0x02 },
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{ S1DREG_CRT_NDISP_VPER, 0x1b },
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{ S1DREG_CRT_VRTC_START, 0x00 },
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{ S1DREG_CRT_VRTC_PWIDTH, 0x83 },
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{ S1DREG_TV_OUT_CTL, 0x10 },
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{ S1DREG_CRT_DISP_MODE, 0x05 },
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{ S1DREG_CRT_DISP_START0, 0x00 },
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{ S1DREG_CRT_DISP_START1, 0x00 },
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{ S1DREG_CRT_DISP_START2, 0x00 },
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{ S1DREG_CRT_MEM_OFF0, 0x20 },
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{ S1DREG_CRT_MEM_OFF1, 0x03 },
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{ S1DREG_CRT_PIX_PAN, 0x00 },
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{ S1DREG_CRT_DISP_FIFO_HTC, 0x00 },
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{ S1DREG_CRT_DISP_FIFO_LTC, 0x00 },
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{ S1DREG_LCD_CUR_CTL, 0x00 },
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{ S1DREG_LCD_CUR_START, 0x01 },
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{ S1DREG_LCD_CUR_XPOS0, 0x00 },
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{ S1DREG_LCD_CUR_XPOS1, 0x00 },
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{ S1DREG_LCD_CUR_YPOS0, 0x00 },
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{ S1DREG_LCD_CUR_YPOS1, 0x00 },
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{ S1DREG_LCD_CUR_BCTL0, 0x00 },
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{ S1DREG_LCD_CUR_GCTL0, 0x00 },
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{ S1DREG_LCD_CUR_RCTL0, 0x00 },
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{ S1DREG_LCD_CUR_BCTL1, 0x1f },
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{ S1DREG_LCD_CUR_GCTL1, 0x3f },
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{ S1DREG_LCD_CUR_RCTL1, 0x1f },
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{ S1DREG_LCD_CUR_FIFO_HTC, 0x00 },
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{ S1DREG_CRT_CUR_CTL, 0x00 },
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{ S1DREG_CRT_CUR_START, 0x01 },
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{ S1DREG_CRT_CUR_XPOS0, 0x00 },
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{ S1DREG_CRT_CUR_XPOS1, 0x00 },
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{ S1DREG_CRT_CUR_YPOS0, 0x00 },
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{ S1DREG_CRT_CUR_YPOS1, 0x00 },
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{ S1DREG_CRT_CUR_BCTL0, 0x00 },
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{ S1DREG_CRT_CUR_GCTL0, 0x00 },
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{ S1DREG_CRT_CUR_RCTL0, 0x00 },
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{ S1DREG_CRT_CUR_BCTL1, 0x1f },
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{ S1DREG_CRT_CUR_GCTL1, 0x3f },
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{ S1DREG_CRT_CUR_RCTL1, 0x1f },
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{ S1DREG_CRT_CUR_FIFO_HTC, 0x00 },
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{ S1DREG_BBLT_CTL0, 0x00 },
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{ S1DREG_BBLT_CTL1, 0x00 },
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{ S1DREG_BBLT_CC_EXP, 0x00 },
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{ S1DREG_BBLT_OP, 0x00 },
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{ S1DREG_BBLT_SRC_START0, 0x00 },
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{ S1DREG_BBLT_SRC_START1, 0x00 },
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{ S1DREG_BBLT_SRC_START2, 0x00 },
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{ S1DREG_BBLT_DST_START0, 0x00 },
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{ S1DREG_BBLT_DST_START1, 0x00 },
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{ S1DREG_BBLT_DST_START2, 0x00 },
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{ S1DREG_BBLT_MEM_OFF0, 0x00 },
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{ S1DREG_BBLT_MEM_OFF1, 0x00 },
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{ S1DREG_BBLT_WIDTH0, 0x00 },
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{ S1DREG_BBLT_WIDTH1, 0x00 },
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{ S1DREG_BBLT_HEIGHT0, 0x00 },
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{ S1DREG_BBLT_HEIGHT1, 0x00 },
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{ S1DREG_BBLT_BGC0, 0x00 },
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{ S1DREG_BBLT_BGC1, 0x00 },
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{ S1DREG_BBLT_FGC0, 0x00 },
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{ S1DREG_BBLT_FGC1, 0x00 },
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{ S1DREG_LKUP_MODE, 0x00 },
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{ S1DREG_LKUP_ADDR, 0x00 },
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{ S1DREG_PS_CNF, 0x10 },
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{ S1DREG_PS_STATUS, 0x00 },
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{ S1DREG_CPU2MEM_WDOGT, 0x00 },
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{ S1DREG_COM_DISP_MODE, 0x02 },
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};
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static struct s1d13xxxfb_pdata s1d13806_platform_data = {
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.initregs = s1d13806_initregs,
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.initregssize = ARRAY_SIZE(s1d13806_initregs),
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};
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static struct resource s1d13806_resources[] = {
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[0] = {
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.start = 0x07200000,
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.end = 0x07200000 + 0x00200000 - 1,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = 0x07000000,
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.end = 0x07000000 + 0x00200000 - 1,
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.flags = IORESOURCE_MEM,
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},
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};
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static struct platform_device s1d13806_device = {
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.name = "s1d13806fb",
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.id = -1,
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.num_resources = ARRAY_SIZE(s1d13806_resources),
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.resource = s1d13806_resources,
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.dev = {
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.platform_data = &s1d13806_platform_data,
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},
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};
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#endif
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static struct platform_device *microdev_devices[] __initdata = {
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&smc91x_device,
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#ifdef CONFIG_FB_S1D13XXX
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&s1d13806_device,
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#endif
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};
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static int __init microdev_devices_setup(void)
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{
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return platform_add_devices(microdev_devices, ARRAY_SIZE(microdev_devices));
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}
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__initcall(microdev_devices_setup);
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void __init platform_setup(void)
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{
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int * const fpgaRevisionRegister = (int*)(MICRODEV_FPGA_GP_BASE + 0x8ul);
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const int fpgaRevision = *fpgaRevisionRegister;
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int * const CacheControlRegister = (int*)CCR;
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printk("SuperH %s board (FPGA rev: 0x%0x, CCR: 0x%0x)\n",
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get_system_type(), fpgaRevision, *CacheControlRegister);
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}
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/****************************************************************************/
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/*
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* Setup for the SMSC FDC37C93xAPM
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*/
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static int __init smsc_superio_setup(void)
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{
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unsigned char devid, devrev;
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/* Initially the chip is in run state */
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/* Put it into configuration state */
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outb(SMSC_ENTER_CONFIG_KEY, SMSC_CONFIG_PORT_ADDR);
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/* Read device ID info */
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devid = SMSC_READ_INDEXED(SMSC_DEVICE_ID_INDEX);
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devrev = SMSC_READ_INDEXED(SMSC_DEVICE_REV_INDEX);
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if ( (devid==0x30) && (devrev==0x01) )
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{
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printk("SMSC FDC37C93xAPM SuperIO device detected\n");
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}
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else
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{ /* not the device identity we expected */
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printk("Not detected a SMSC FDC37C93xAPM SuperIO device (devid=0x%02x, rev=0x%02x)\n",
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devid, devrev);
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/* inform the keyboard driver that we have no keyboard controller */
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microdev_kbd_controller_present = 0;
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/* little point in doing anything else in this functon */
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return 0;
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}
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/* Select the keyboard device */
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SMSC_WRITE_INDEXED(SMSC_KEYBOARD_DEVICE, SMCS_LOGICAL_DEV_INDEX);
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/* enable it */
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SMSC_WRITE_INDEXED(1, SMSC_ACTIVATE_INDEX);
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/* enable the interrupts */
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SMSC_WRITE_INDEXED(MICRODEV_FPGA_IRQ_KEYBOARD, SMSC_PRIMARY_INT_INDEX);
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SMSC_WRITE_INDEXED(MICRODEV_FPGA_IRQ_MOUSE, SMSC_SECONDARY_INT_INDEX);
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/* Select the Serial #1 device */
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SMSC_WRITE_INDEXED(SMSC_SERIAL1_DEVICE, SMCS_LOGICAL_DEV_INDEX);
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/* enable it */
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SMSC_WRITE_INDEXED(1, SMSC_ACTIVATE_INDEX);
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/* program with port addresses */
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SMSC_WRITE_INDEXED(MSB(SERIAL1_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+0);
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SMSC_WRITE_INDEXED(LSB(SERIAL1_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+1);
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SMSC_WRITE_INDEXED(0x00, SMSC_HDCS0_INDEX);
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/* enable the interrupts */
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SMSC_WRITE_INDEXED(MICRODEV_FPGA_IRQ_SERIAL1, SMSC_PRIMARY_INT_INDEX);
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/* Select the Serial #2 device */
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SMSC_WRITE_INDEXED(SMSC_SERIAL2_DEVICE, SMCS_LOGICAL_DEV_INDEX);
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/* enable it */
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SMSC_WRITE_INDEXED(1, SMSC_ACTIVATE_INDEX);
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/* program with port addresses */
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SMSC_WRITE_INDEXED(MSB(SERIAL2_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+0);
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SMSC_WRITE_INDEXED(LSB(SERIAL2_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+1);
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SMSC_WRITE_INDEXED(0x00, SMSC_HDCS0_INDEX);
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/* enable the interrupts */
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SMSC_WRITE_INDEXED(MICRODEV_FPGA_IRQ_SERIAL2, SMSC_PRIMARY_INT_INDEX);
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/* Select the IDE#1 device */
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SMSC_WRITE_INDEXED(SMSC_IDE1_DEVICE, SMCS_LOGICAL_DEV_INDEX);
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/* enable it */
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SMSC_WRITE_INDEXED(1, SMSC_ACTIVATE_INDEX);
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/* program with port addresses */
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SMSC_WRITE_INDEXED(MSB(IDE1_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+0);
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SMSC_WRITE_INDEXED(LSB(IDE1_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+1);
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SMSC_WRITE_INDEXED(MSB(IDE1_SECONDARY_BASE), SMSC_SECONDARY_BASE_INDEX+0);
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SMSC_WRITE_INDEXED(LSB(IDE1_SECONDARY_BASE), SMSC_SECONDARY_BASE_INDEX+1);
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SMSC_WRITE_INDEXED(0x0c, SMSC_HDCS0_INDEX);
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SMSC_WRITE_INDEXED(0x00, SMSC_HDCS1_INDEX);
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/* select the interrupt */
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SMSC_WRITE_INDEXED(MICRODEV_FPGA_IRQ_IDE1, SMSC_PRIMARY_INT_INDEX);
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/* Select the IDE#2 device */
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SMSC_WRITE_INDEXED(SMSC_IDE2_DEVICE, SMCS_LOGICAL_DEV_INDEX);
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/* enable it */
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SMSC_WRITE_INDEXED(1, SMSC_ACTIVATE_INDEX);
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/* program with port addresses */
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SMSC_WRITE_INDEXED(MSB(IDE2_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+0);
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SMSC_WRITE_INDEXED(LSB(IDE2_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+1);
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SMSC_WRITE_INDEXED(MSB(IDE2_SECONDARY_BASE), SMSC_SECONDARY_BASE_INDEX+0);
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SMSC_WRITE_INDEXED(LSB(IDE2_SECONDARY_BASE), SMSC_SECONDARY_BASE_INDEX+1);
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/* select the interrupt */
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SMSC_WRITE_INDEXED(MICRODEV_FPGA_IRQ_IDE2, SMSC_PRIMARY_INT_INDEX);
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/* Select the configuration registers */
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SMSC_WRITE_INDEXED(SMSC_CONFIG_REGISTERS, SMCS_LOGICAL_DEV_INDEX);
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/* enable the appropriate GPIO pins for IDE functionality:
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* bit[0] In/Out 1==input; 0==output
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* bit[1] Polarity 1==invert; 0==no invert
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* bit[2] Int Enb #1 1==Enable Combined IRQ #1; 0==disable
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* bit[3:4] Function Select 00==original; 01==Alternate Function #1
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*/
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SMSC_WRITE_INDEXED(0x00, 0xc2); /* GP42 = nIDE1_OE */
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SMSC_WRITE_INDEXED(0x01, 0xc5); /* GP45 = IDE1_IRQ */
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SMSC_WRITE_INDEXED(0x00, 0xc6); /* GP46 = nIOROP */
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SMSC_WRITE_INDEXED(0x00, 0xc7); /* GP47 = nIOWOP */
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SMSC_WRITE_INDEXED(0x08, 0xe8); /* GP20 = nIDE2_OE */
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|
|
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/* Exit the configuraton state */
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outb(SMSC_EXIT_CONFIG_KEY, SMSC_CONFIG_PORT_ADDR);
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|
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return 0;
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}
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|
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/* This is grotty, but, because kernel is always referenced on the link line
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|
* before any devices, this is safe.
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|
*/
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__initcall(smsc_superio_setup);
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