92 lines
3.4 KiB
C
92 lines
3.4 KiB
C
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/*
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* Copyright (c) 2009 ST-Ericsson SA
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2
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* as published by the Free Software Foundation.
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*/
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#ifndef __MACH_PRCMU_REGS_H
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#define __MACH_PRCMU_REGS_H
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#include <mach/hardware.h>
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#define _PRCMU_BASE IO_ADDRESS(U8500_PRCMU_BASE)
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#define PRCM_ARM_PLLDIVPS (_PRCMU_BASE + 0x118)
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#define PRCM_ARM_CHGCLKREQ (_PRCMU_BASE + 0x114)
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#define PRCM_PLLARM_ENABLE (_PRCMU_BASE + 0x98)
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#define PRCM_ARMCLKFIX_MGT (_PRCMU_BASE + 0x0)
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#define PRCM_A9_RESETN_CLR (_PRCMU_BASE + 0x1f4)
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#define PRCM_A9_RESETN_SET (_PRCMU_BASE + 0x1f0)
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#define PRCM_ARM_LS_CLAMP (_PRCMU_BASE + 0x30c)
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#define PRCM_SRAM_A9 (_PRCMU_BASE + 0x308)
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/* ARM WFI Standby signal register */
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#define PRCM_ARM_WFI_STANDBY (_PRCMU_BASE + 0x130)
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#define PRCMU_IOCR (_PRCMU_BASE + 0x310)
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/* CPU mailbox registers */
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#define PRCM_MBOX_CPU_VAL (_PRCMU_BASE + 0x0fc)
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#define PRCM_MBOX_CPU_SET (_PRCMU_BASE + 0x100)
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#define PRCM_MBOX_CPU_CLR (_PRCMU_BASE + 0x104)
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/* Dual A9 core interrupt management unit registers */
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#define PRCM_A9_MASK_REQ (_PRCMU_BASE + 0x328)
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#define PRCM_A9_MASK_ACK (_PRCMU_BASE + 0x32c)
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#define PRCM_ARMITMSK31TO0 (_PRCMU_BASE + 0x11c)
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#define PRCM_ARMITMSK63TO32 (_PRCMU_BASE + 0x120)
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#define PRCM_ARMITMSK95TO64 (_PRCMU_BASE + 0x124)
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#define PRCM_ARMITMSK127TO96 (_PRCMU_BASE + 0x128)
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#define PRCM_POWER_STATE_VAL (_PRCMU_BASE + 0x25C)
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#define PRCM_ARMITVAL31TO0 (_PRCMU_BASE + 0x260)
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#define PRCM_ARMITVAL63TO32 (_PRCMU_BASE + 0x264)
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#define PRCM_ARMITVAL95TO64 (_PRCMU_BASE + 0x268)
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#define PRCM_ARMITVAL127TO96 (_PRCMU_BASE + 0x26C)
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#define PRCM_HOSTACCESS_REQ (_PRCMU_BASE + 0x334)
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#define ARM_WAKEUP_MODEM 0x1
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#define PRCM_ARM_IT1_CLEAR (_PRCMU_BASE + 0x48C)
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#define PRCM_ARM_IT1_VAL (_PRCMU_BASE + 0x494)
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#define PRCM_HOLD_EVT (_PRCMU_BASE + 0x174)
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#define PRCM_ITSTATUS0 (_PRCMU_BASE + 0x148)
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#define PRCM_ITSTATUS1 (_PRCMU_BASE + 0x150)
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#define PRCM_ITSTATUS2 (_PRCMU_BASE + 0x158)
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#define PRCM_ITSTATUS3 (_PRCMU_BASE + 0x160)
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#define PRCM_ITSTATUS4 (_PRCMU_BASE + 0x168)
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#define PRCM_ITSTATUS5 (_PRCMU_BASE + 0x484)
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#define PRCM_ITCLEAR5 (_PRCMU_BASE + 0x488)
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#define PRCM_ARMIT_MASKXP70_IT (_PRCMU_BASE + 0x1018)
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/* System reset register */
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#define PRCM_APE_SOFTRST (_PRCMU_BASE + 0x228)
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/* Level shifter and clamp control registers */
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#define PRCM_MMIP_LS_CLAMP_SET (_PRCMU_BASE + 0x420)
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#define PRCM_MMIP_LS_CLAMP_CLR (_PRCMU_BASE + 0x424)
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/* PRCMU clock/PLL/reset registers */
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#define PRCM_PLLDSI_FREQ (_PRCMU_BASE + 0x500)
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#define PRCM_PLLDSI_ENABLE (_PRCMU_BASE + 0x504)
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#define PRCM_LCDCLK_MGT (_PRCMU_BASE + 0x044)
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#define PRCM_MCDECLK_MGT (_PRCMU_BASE + 0x064)
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#define PRCM_HDMICLK_MGT (_PRCMU_BASE + 0x058)
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#define PRCM_TVCLK_MGT (_PRCMU_BASE + 0x07c)
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#define PRCM_DSI_PLLOUT_SEL (_PRCMU_BASE + 0x530)
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#define PRCM_DSITVCLK_DIV (_PRCMU_BASE + 0x52C)
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#define PRCM_APE_RESETN_SET (_PRCMU_BASE + 0x1E4)
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#define PRCM_APE_RESETN_CLR (_PRCMU_BASE + 0x1E8)
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/* ePOD and memory power signal control registers */
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#define PRCM_EPOD_C_SET (_PRCMU_BASE + 0x410)
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#define PRCM_SRAM_LS_SLEEP (_PRCMU_BASE + 0x304)
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/* Debug power control unit registers */
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#define PRCM_POWER_STATE_SET (_PRCMU_BASE + 0x254)
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/* Miscellaneous unit registers */
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#define PRCM_DSI_SW_RESET (_PRCMU_BASE + 0x324)
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#endif /* __MACH_PRCMU__REGS_H */
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