60 lines
1.5 KiB
C
60 lines
1.5 KiB
C
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/*
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* l2 cache initialization for CSR SiRFprimaII
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*
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* Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
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*
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* Licensed under GPLv2 or later.
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/io.h>
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#include <linux/errno.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <asm/hardware/cache-l2x0.h>
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#include <mach/memory.h>
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#define L2X0_ADDR_FILTERING_START 0xC00
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#define L2X0_ADDR_FILTERING_END 0xC04
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static struct of_device_id l2x_ids[] = {
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{ .compatible = "arm,pl310-cache" },
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};
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static int __init sirfsoc_of_l2x_init(void)
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{
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struct device_node *np;
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void __iomem *sirfsoc_l2x_base;
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np = of_find_matching_node(NULL, l2x_ids);
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if (!np)
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panic("unable to find compatible l2x node in dtb\n");
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sirfsoc_l2x_base = of_iomap(np, 0);
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if (!sirfsoc_l2x_base)
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panic("unable to map l2x cpu registers\n");
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of_node_put(np);
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if (!(readl_relaxed(sirfsoc_l2x_base + L2X0_CTRL) & 1)) {
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/*
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* set the physical memory windows L2 cache will cover
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*/
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writel_relaxed(PLAT_PHYS_OFFSET + 1024 * 1024 * 1024,
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sirfsoc_l2x_base + L2X0_ADDR_FILTERING_END);
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writel_relaxed(PLAT_PHYS_OFFSET | 0x1,
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sirfsoc_l2x_base + L2X0_ADDR_FILTERING_START);
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writel_relaxed(0,
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sirfsoc_l2x_base + L2X0_TAG_LATENCY_CTRL);
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writel_relaxed(0,
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sirfsoc_l2x_base + L2X0_DATA_LATENCY_CTRL);
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}
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l2x0_init((void __iomem *)sirfsoc_l2x_base, 0x00040000,
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0x00000000);
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return 0;
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}
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early_initcall(sirfsoc_of_l2x_init);
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