54 lines
1.2 KiB
C
54 lines
1.2 KiB
C
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/bitops.h>
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#include <asm/processor.h>
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#include "cpu.h"
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static void __init init_rise(struct cpuinfo_x86 *c)
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{
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printk("CPU: Rise iDragon");
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if (c->x86_model > 2)
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printk(" II");
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printk("\n");
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/* Unhide possibly hidden capability flags
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The mp6 iDragon family don't have MSRs.
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We switch on extra features with this cpuid weirdness: */
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__asm__ (
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"movl $0x6363452a, %%eax\n\t"
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"movl $0x3231206c, %%ecx\n\t"
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"movl $0x2a32313a, %%edx\n\t"
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"cpuid\n\t"
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"movl $0x63634523, %%eax\n\t"
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"movl $0x32315f6c, %%ecx\n\t"
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"movl $0x2333313a, %%edx\n\t"
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"cpuid\n\t" : : : "eax", "ebx", "ecx", "edx"
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);
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set_bit(X86_FEATURE_CX8, c->x86_capability);
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}
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static struct cpu_dev rise_cpu_dev __initdata = {
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.c_vendor = "Rise",
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.c_ident = { "RiseRiseRise" },
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.c_models = {
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{ .vendor = X86_VENDOR_RISE, .family = 5, .model_names =
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{
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[0] = "iDragon",
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[2] = "iDragon",
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[8] = "iDragon II",
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[9] = "iDragon II"
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}
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},
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},
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.c_init = init_rise,
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};
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int __init rise_init_cpu(void)
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{
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cpu_devs[X86_VENDOR_RISE] = &rise_cpu_dev;
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return 0;
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}
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//early_arch_initcall(rise_init_cpu);
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