52 lines
1.4 KiB
Plaintext
52 lines
1.4 KiB
Plaintext
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Davinci SPI controller device bindings
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Required properties:
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- #address-cells: number of cells required to define a chip select
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address on the SPI bus. Should be set to 1.
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- #size-cells: should be zero.
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- compatible:
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- "ti,dm6441-spi" for SPI used similar to that on DM644x SoC family
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- "ti,da830-spi" for SPI used similar to that on DA8xx SoC family
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- reg: Offset and length of SPI controller register space
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- num-cs: Number of chip selects
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- ti,davinci-spi-intr-line: interrupt line used to connect the SPI
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IP to the interrupt controller within the SoC. Possible values
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are 0 and 1. Manual says one of the two possible interrupt
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lines can be tied to the interrupt controller. Set this
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based on a specifc SoC configuration.
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- interrupts: interrupt number mapped to CPU.
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- clocks: spi clk phandle
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Example of a NOR flash slave device (n25q032) connected to DaVinci
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SPI controller device over the SPI bus.
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spi0:spi@20BF0000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "ti,dm6446-spi";
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reg = <0x20BF0000 0x1000>;
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num-cs = <4>;
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ti,davinci-spi-intr-line = <0>;
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interrupts = <338>;
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clocks = <&clkspi>;
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flash: n25q032@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "st,m25p32";
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spi-max-frequency = <25000000>;
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reg = <0>;
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partition@0 {
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label = "u-boot-spl";
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reg = <0x0 0x80000>;
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read-only;
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};
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partition@1 {
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label = "test";
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reg = <0x80000 0x380000>;
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};
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};
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};
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