130 lines
4.2 KiB
C
130 lines
4.2 KiB
C
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/*
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* arch/ppc/platforms/chestnut.h
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*
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* Definitions for IBM 750FXGX Eval (Chestnut)
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*
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* Author: <source@mvista.com>
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*
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* Based on Artesyn Katana code done by Tim Montgomery <timm@artesyncp.com>
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* Based on code done by Rabeeh Khoury - rabeeh@galileo.co.il
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* Based on code done by Mark A. Greer <mgreer@mvista.com>
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*
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* <2004> (c) MontaVista Software, Inc. This file is licensed under
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* the terms of the GNU General Public License version 2. This program
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* is licensed "as is" without any warranty of any kind, whether express
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* or implied.
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*/
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/*
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* This is the CPU physical memory map (windows must be at least 1MB and start
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* on a boundary that is a multiple of the window size):
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*
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* Seems on the IBM 750FXGX Eval board, the MV64460 Registers can be in
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* only 2 places per switch U17 0x14000000 or 0xf1000000 easily - chose to
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* implement at 0xf1000000 only at this time
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*
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* 0xfff00000-0xffffffff - 8 Flash
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* 0xffe00000-0xffefffff - BOOT SRAM
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* 0xffd00000-0xffd00004 - CPLD
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* 0xffc00000-0xffc0000f - UART
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* 0xffb00000-0xffb07fff - FRAM
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* 0xff840000-0xffafffff - *** HOLE ***
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* 0xff800000-0xff83ffff - MV64460 Integrated SRAM
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* 0xfe000000-0xff8fffff - *** HOLE ***
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* 0xfc000000-0xfdffffff - 32bit Flash
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* 0xf1010000-0xfbffffff - *** HOLE ***
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* 0xf1000000-0xf100ffff - MV64460 Registers
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*/
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#ifndef __PPC_PLATFORMS_CHESTNUT_H__
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#define __PPC_PLATFORMS_CHESTNUT_H__
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#define CHESTNUT_BOOT_8BIT_BASE 0xfff00000
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#define CHESTNUT_BOOT_8BIT_SIZE_ACTUAL (1024*1024)
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#define CHESTNUT_BOOT_SRAM_BASE 0xffe00000
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#define CHESTNUT_BOOT_SRAM_SIZE_ACTUAL (1024*1024)
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#define CHESTNUT_CPLD_BASE 0xffd00000
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#define CHESTNUT_CPLD_SIZE_ACTUAL 5
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#define CHESTNUT_CPLD_REG3 (CHESTNUT_CPLD_BASE+3)
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#define CHESTNUT_UART_BASE 0xffc00000
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#define CHESTNUT_UART_SIZE_ACTUAL 16
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#define CHESTNUT_FRAM_BASE 0xffb00000
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#define CHESTNUT_FRAM_SIZE_ACTUAL (32*1024)
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#define CHESTNUT_INTERNAL_SRAM_BASE 0xff800000
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#define CHESTNUT_32BIT_BASE 0xfc000000
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#define CHESTNUT_32BIT_SIZE (32*1024*1024)
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#define CHESTNUT_BOOT_8BIT_SIZE max(MV64360_WINDOW_SIZE_MIN, \
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CHESTNUT_BOOT_8BIT_SIZE_ACTUAL)
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#define CHESTNUT_BOOT_SRAM_SIZE max(MV64360_WINDOW_SIZE_MIN, \
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CHESTNUT_BOOT_SRAM_SIZE_ACTUAL)
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#define CHESTNUT_CPLD_SIZE max(MV64360_WINDOW_SIZE_MIN, \
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CHESTNUT_CPLD_SIZE_ACTUAL)
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#define CHESTNUT_UART_SIZE max(MV64360_WINDOW_SIZE_MIN, \
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CHESTNUT_UART_SIZE_ACTUAL)
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#define CHESTNUT_FRAM_SIZE max(MV64360_WINDOW_SIZE_MIN, \
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CHESTNUT_FRAM_SIZE_ACTUAL)
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#define CHESTNUT_BUS_SPEED 200000000
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#define CHESTNUT_PIBS_DATABASE 0xf0000 /* from PIBS src code */
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#define KATANA_ETH0_PHY_ADDR 12
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#define KATANA_ETH1_PHY_ADDR 11
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#define KATANA_ETH2_PHY_ADDR 4
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#define CHESTNUT_ETH_TX_QUEUE_SIZE 800
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#define CHESTNUT_ETH_RX_QUEUE_SIZE 400
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/*
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* PCI windows
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*/
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#define CHESTNUT_PCI0_MEM_PROC_ADDR 0x80000000
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#define CHESTNUT_PCI0_MEM_PCI_HI_ADDR 0x00000000
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#define CHESTNUT_PCI0_MEM_PCI_LO_ADDR 0x80000000
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#define CHESTNUT_PCI0_MEM_SIZE 0x10000000
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#define CHESTNUT_PCI0_IO_PROC_ADDR 0xa0000000
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#define CHESTNUT_PCI0_IO_PCI_ADDR 0x00000000
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#define CHESTNUT_PCI0_IO_SIZE 0x01000000
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/*
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* Board-specific IRQ info
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*/
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#define CHESTNUT_PCI_SLOT0_IRQ (64 + 31)
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#define CHESTNUT_PCI_SLOT1_IRQ (64 + 30)
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#define CHESTNUT_PCI_SLOT2_IRQ (64 + 29)
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#define CHESTNUT_PCI_SLOT3_IRQ (64 + 28)
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/* serial port definitions */
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#define CHESTNUT_UART0_IO_BASE (CHESTNUT_UART_BASE + 8)
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#define CHESTNUT_UART1_IO_BASE CHESTNUT_UART_BASE
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#define UART0_INT (64 + 25)
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#define UART1_INT (64 + 26)
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#ifdef CONFIG_SERIAL_MANY_PORTS
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#define RS_TABLE_SIZE 64
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#else
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#define RS_TABLE_SIZE 2
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#endif
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/* Rate for the 3.6864 Mhz clock for the onboard serial chip */
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#define BASE_BAUD (3686400 / 16)
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#ifdef CONFIG_SERIAL_DETECT_IRQ
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#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF|ASYNC_SKIP_TEST|ASYNC_AUTO_IRQ)
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#else
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#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF|ASYNC_SKIP_TEST)
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#endif
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#define STD_UART_OP(num) \
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{ 0, BASE_BAUD, 0, UART##num##_INT, STD_COM_FLAGS, \
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iomem_base: (u8 *)CHESTNUT_UART##num##_IO_BASE, \
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io_type: SERIAL_IO_MEM},
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#define SERIAL_PORT_DFNS \
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STD_UART_OP(0) \
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STD_UART_OP(1)
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#endif /* __PPC_PLATFORMS_CHESTNUT_H__ */
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