2005-04-17 06:20:36 +08:00
|
|
|
/*
|
2008-08-05 23:14:15 +08:00
|
|
|
* arch/arm/mach-sa1100/include/mach/memory.h
|
2005-04-17 06:20:36 +08:00
|
|
|
*
|
|
|
|
* Copyright (C) 1999-2000 Nicolas Pitre <nico@cam.org>
|
|
|
|
*/
|
|
|
|
|
|
|
|
#ifndef __ASM_ARCH_MEMORY_H
|
|
|
|
#define __ASM_ARCH_MEMORY_H
|
|
|
|
|
|
|
|
#include <asm/sizes.h>
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Physical DRAM offset is 0xc0000000 on the SA1100
|
|
|
|
*/
|
2005-10-30 04:44:55 +08:00
|
|
|
#define PHYS_OFFSET UL(0xc0000000)
|
2005-04-17 06:20:36 +08:00
|
|
|
|
|
|
|
#ifndef __ASSEMBLY__
|
|
|
|
|
|
|
|
#ifdef CONFIG_SA1111
|
2005-11-17 01:38:40 +08:00
|
|
|
void sa1111_adjust_zones(int node, unsigned long *size, unsigned long *holes);
|
2005-04-17 06:20:36 +08:00
|
|
|
|
|
|
|
#define arch_adjust_zones(node, size, holes) \
|
2005-11-17 01:38:40 +08:00
|
|
|
sa1111_adjust_zones(node, size, holes)
|
2005-04-17 06:20:36 +08:00
|
|
|
|
|
|
|
#define ISA_DMA_THRESHOLD (PHYS_OFFSET + SZ_1M - 1)
|
2008-11-30 21:26:47 +08:00
|
|
|
#define MAX_DMA_ADDRESS (PAGE_OFFSET + SZ_1M)
|
2005-04-17 06:20:36 +08:00
|
|
|
|
|
|
|
#endif
|
|
|
|
#endif
|
|
|
|
|
|
|
|
/*
|
2008-10-02 04:03:21 +08:00
|
|
|
* Because of the wide memory address space between physical RAM banks on the
|
|
|
|
* SA1100, it's much convenient to use Linux's SparseMEM support to implement
|
|
|
|
* our memory map representation. Assuming all memory nodes have equal access
|
2005-04-17 06:20:36 +08:00
|
|
|
* characteristics, we then have generic discontiguous memory support.
|
|
|
|
*
|
2008-10-02 04:03:21 +08:00
|
|
|
* The sparsemem banks are matched with the physical memory bank addresses
|
|
|
|
* which are incidentally the same as virtual addresses.
|
2005-04-17 06:20:36 +08:00
|
|
|
*
|
|
|
|
* node 0: 0xc0000000 - 0xc7ffffff
|
|
|
|
* node 1: 0xc8000000 - 0xcfffffff
|
|
|
|
* node 2: 0xd0000000 - 0xd7ffffff
|
|
|
|
* node 3: 0xd8000000 - 0xdfffffff
|
|
|
|
*/
|
2008-10-02 04:03:21 +08:00
|
|
|
#define MAX_PHYSMEM_BITS 32
|
|
|
|
#define SECTION_SIZE_BITS 27
|
2005-04-17 06:20:36 +08:00
|
|
|
|
2006-04-05 04:47:43 +08:00
|
|
|
/*
|
|
|
|
* Cache flushing area - SA1100 zero bank
|
|
|
|
*/
|
|
|
|
#define FLUSH_BASE_PHYS 0xe0000000
|
|
|
|
#define FLUSH_BASE 0xf5000000
|
|
|
|
#define FLUSH_BASE_MINICACHE 0xf5100000
|
|
|
|
|
2005-04-17 06:20:36 +08:00
|
|
|
#endif
|