115 lines
3.2 KiB
C
115 lines
3.2 KiB
C
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/*
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* EDAC defs for Marvell MV64x60 bridge chip
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*
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* Author: Dave Jiang <djiang@mvista.com>
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*
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* 2007 (c) MontaVista Software, Inc. This file is licensed under
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* the terms of the GNU General Public License version 2. This program
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* is licensed "as is" without any warranty of any kind, whether express
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* or implied.
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*
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*/
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#ifndef _MV64X60_EDAC_H_
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#define _MV64X60_EDAC_H_
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#define MV64x60_REVISION " Ver: 2.0.0 " __DATE__
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#define EDAC_MOD_STR "MV64x60_edac"
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#define mv64x60_printk(level, fmt, arg...) \
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edac_printk(level, "MV64x60", fmt, ##arg)
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#define mv64x60_mc_printk(mci, level, fmt, arg...) \
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edac_mc_chipset_printk(mci, level, "MV64x60", fmt, ##arg)
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/* CPU Error Report Registers */
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#define MV64x60_CPU_ERR_ADDR_LO 0x00 /* 0x0070 */
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#define MV64x60_CPU_ERR_ADDR_HI 0x08 /* 0x0078 */
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#define MV64x60_CPU_ERR_DATA_LO 0x00 /* 0x0128 */
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#define MV64x60_CPU_ERR_DATA_HI 0x08 /* 0x0130 */
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#define MV64x60_CPU_ERR_PARITY 0x10 /* 0x0138 */
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#define MV64x60_CPU_ERR_CAUSE 0x18 /* 0x0140 */
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#define MV64x60_CPU_ERR_MASK 0x20 /* 0x0148 */
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#define MV64x60_CPU_CAUSE_MASK 0x07ffffff
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/* SRAM Error Report Registers */
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#define MV64X60_SRAM_ERR_CAUSE 0x08 /* 0x0388 */
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#define MV64X60_SRAM_ERR_ADDR_LO 0x10 /* 0x0390 */
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#define MV64X60_SRAM_ERR_ADDR_HI 0x78 /* 0x03f8 */
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#define MV64X60_SRAM_ERR_DATA_LO 0x18 /* 0x0398 */
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#define MV64X60_SRAM_ERR_DATA_HI 0x20 /* 0x03a0 */
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#define MV64X60_SRAM_ERR_PARITY 0x28 /* 0x03a8 */
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/* SDRAM Controller Registers */
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#define MV64X60_SDRAM_CONFIG 0x00 /* 0x1400 */
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#define MV64X60_SDRAM_ERR_DATA_HI 0x40 /* 0x1440 */
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#define MV64X60_SDRAM_ERR_DATA_LO 0x44 /* 0x1444 */
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#define MV64X60_SDRAM_ERR_ECC_RCVD 0x48 /* 0x1448 */
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#define MV64X60_SDRAM_ERR_ECC_CALC 0x4c /* 0x144c */
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#define MV64X60_SDRAM_ERR_ADDR 0x50 /* 0x1450 */
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#define MV64X60_SDRAM_ERR_ECC_CNTL 0x54 /* 0x1454 */
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#define MV64X60_SDRAM_ERR_ECC_ERR_CNT 0x58 /* 0x1458 */
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#define MV64X60_SDRAM_REGISTERED 0x20000
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#define MV64X60_SDRAM_ECC 0x40000
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#ifdef CONFIG_PCI
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/*
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* Bit 0 of MV64x60_PCIx_ERR_MASK does not exist on the 64360 and because of
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* errata FEr-#11 and FEr-##16 for the 64460, it should be 0 on that chip as
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* well. IOW, don't set bit 0.
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*/
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#define MV64X60_PCIx_ERR_MASK_VAL 0x00a50c24
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/* Register offsets from PCIx error address low register */
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#define MV64X60_PCI_ERROR_ADDR_LO 0x00
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#define MV64X60_PCI_ERROR_ADDR_HI 0x04
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#define MV64X60_PCI_ERROR_ATTR 0x08
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#define MV64X60_PCI_ERROR_CMD 0x10
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#define MV64X60_PCI_ERROR_CAUSE 0x18
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#define MV64X60_PCI_ERROR_MASK 0x1c
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#define MV64X60_PCI_ERR_SWrPerr 0x0002
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#define MV64X60_PCI_ERR_SRdPerr 0x0004
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#define MV64X60_PCI_ERR_MWrPerr 0x0020
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#define MV64X60_PCI_ERR_MRdPerr 0x0040
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#define MV64X60_PCI_PE_MASK (MV64X60_PCI_ERR_SWrPerr | \
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MV64X60_PCI_ERR_SRdPerr | \
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MV64X60_PCI_ERR_MWrPerr | \
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MV64X60_PCI_ERR_MRdPerr)
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struct mv64x60_pci_pdata {
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int pci_hose;
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void __iomem *pci_vbase;
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char *name;
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int irq;
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int edac_idx;
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};
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#endif /* CONFIG_PCI */
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struct mv64x60_mc_pdata {
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void __iomem *mc_vbase;
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int total_mem;
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char *name;
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int irq;
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int edac_idx;
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};
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struct mv64x60_cpu_pdata {
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void __iomem *cpu_vbase[2];
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char *name;
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int irq;
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int edac_idx;
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};
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struct mv64x60_sram_pdata {
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void __iomem *sram_vbase;
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char *name;
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int irq;
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int edac_idx;
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};
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#endif
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