2005-04-17 06:20:36 +08:00
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/*
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* Definitions for Motorola MCG Falcon/Raven & HAWK North Bridge & Memory ctlr.
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*
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* Author: Mark A. Greerinclude/asm-ppc/hawk.h
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* mgreer@mvista.com
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*
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* Modified by Randy Vinson (rvinson@mvista.com)
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*
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* 2001-2004 (c) MontaVista, Software, Inc. This file is licensed under
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* the terms of the GNU General Public License version 2. This program
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* is licensed "as is" without any warranty of any kind, whether express
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* or implied.
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*/
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#ifndef __PPC_PPLUS_H
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#define __PPC_PPLUS_H
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#include <asm/io.h>
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/*
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2007-05-12 03:42:54 +08:00
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* Due to limitations imposed by legacy hardware (primarily IDE controllers),
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2005-04-17 06:20:36 +08:00
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* the PPLUS boards operate using a PReP address map.
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*
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* From Processor (physical) -> PCI:
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* PCI Mem Space: 0xc0000000 - 0xfe000000 -> 0x00000000 - 0x3e000000 (768 MB)
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* PCI I/O Space: 0x80000000 - 0x90000000 -> 0x00000000 - 0x10000000 (256 MB)
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* Note: Must skip 0xfe000000-0xfe400000 for CONFIG_HIGHMEM/PKMAP area
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*
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* From PCI -> Processor (physical):
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* System Memory: 0x80000000 -> 0x00000000
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*/
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#define PPLUS_ISA_MEM_BASE PREP_ISA_MEM_BASE
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#define PPLUS_ISA_IO_BASE PREP_ISA_IO_BASE
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/* PCI Memory space mapping info */
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#define PPLUS_PCI_MEM_SIZE 0x30000000U
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#define PPLUS_PROC_PCI_MEM_START PPLUS_ISA_MEM_BASE
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#define PPLUS_PROC_PCI_MEM_END (PPLUS_PROC_PCI_MEM_START + \
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PPLUS_PCI_MEM_SIZE - 1)
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#define PPLUS_PCI_MEM_START 0x00000000U
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#define PPLUS_PCI_MEM_END (PPLUS_PCI_MEM_START + \
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PPLUS_PCI_MEM_SIZE - 1)
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/* PCI I/O space mapping info */
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#define PPLUS_PCI_IO_SIZE 0x10000000U
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#define PPLUS_PROC_PCI_IO_START PPLUS_ISA_IO_BASE
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#define PPLUS_PROC_PCI_IO_END (PPLUS_PROC_PCI_IO_START + \
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PPLUS_PCI_IO_SIZE - 1)
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#define PPLUS_PCI_IO_START 0x00000000U
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#define PPLUS_PCI_IO_END (PPLUS_PCI_IO_START + \
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PPLUS_PCI_IO_SIZE - 1)
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/* System memory mapping info */
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#define PPLUS_PCI_DRAM_OFFSET PREP_PCI_DRAM_OFFSET
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#define PPLUS_PCI_PHY_MEM_OFFSET (PPLUS_ISA_MEM_BASE-PPLUS_PCI_MEM_START)
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/* Define base addresses for important sets of registers */
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#define PPLUS_HAWK_SMC_BASE 0xfef80000U
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#define PPLUS_HAWK_PPC_REG_BASE 0xfeff0000U
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#define PPLUS_SYS_CONFIG_REG 0xfef80400U
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#define PPLUS_L2_CONTROL_REG 0x8000081cU
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#define PPLUS_VGA_MEM_BASE 0xf0000000U
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#endif /* __PPC_PPLUS_H */
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