2021-06-16 07:18:17 +08:00
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// SPDX-License-Identifier: GPL-2.0-only
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/* Copyright(c) 2021 Intel Corporation. All rights reserved. */
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#include <linux/libnvdimm.h>
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2021-09-10 06:08:15 +08:00
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#include <asm/unaligned.h>
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2021-06-16 07:18:17 +08:00
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#include <linux/device.h>
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#include <linux/module.h>
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2021-06-16 07:36:31 +08:00
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#include <linux/ndctl.h>
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#include <linux/async.h>
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2021-06-16 07:18:17 +08:00
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#include <linux/slab.h>
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2021-08-03 01:29:38 +08:00
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#include "cxlmem.h"
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2021-06-16 07:18:17 +08:00
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#include "cxl.h"
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/*
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* Ordered workqueue for cxl nvdimm device arrival and departure
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* to coordinate bus rescans when a bridge arrives and trigger remove
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* operations when the bridge is removed.
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*/
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static struct workqueue_struct *cxl_pmem_wq;
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2021-09-15 03:03:04 +08:00
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static __read_mostly DECLARE_BITMAP(exclusive_cmds, CXL_MEM_COMMAND_ID_MAX);
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2021-11-03 04:29:01 +08:00
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static void clear_exclusive(void *cxlds)
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2021-09-15 03:03:04 +08:00
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{
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2021-11-03 04:29:01 +08:00
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clear_exclusive_cxl_commands(cxlds, exclusive_cmds);
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2021-09-15 03:03:04 +08:00
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}
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2021-06-16 07:36:31 +08:00
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static void unregister_nvdimm(void *nvdimm)
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{
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nvdimm_delete(nvdimm);
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}
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static int cxl_nvdimm_probe(struct device *dev)
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{
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struct cxl_nvdimm *cxl_nvd = to_cxl_nvdimm(dev);
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2021-09-15 03:03:04 +08:00
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struct cxl_memdev *cxlmd = cxl_nvd->cxlmd;
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2021-09-10 06:08:15 +08:00
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unsigned long flags = 0, cmd_mask = 0;
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2021-11-03 04:29:01 +08:00
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struct cxl_dev_state *cxlds = cxlmd->cxlds;
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2021-06-16 07:36:31 +08:00
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struct cxl_nvdimm_bridge *cxl_nvb;
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struct nvdimm *nvdimm;
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2021-09-15 03:03:04 +08:00
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int rc;
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2021-06-16 07:36:31 +08:00
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2021-09-09 13:13:21 +08:00
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cxl_nvb = cxl_find_nvdimm_bridge(cxl_nvd);
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2021-06-16 07:36:31 +08:00
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if (!cxl_nvb)
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return -ENXIO;
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device_lock(&cxl_nvb->dev);
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2021-09-15 03:03:04 +08:00
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if (!cxl_nvb->nvdimm_bus) {
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rc = -ENXIO;
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goto out;
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}
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2021-11-03 04:29:01 +08:00
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set_exclusive_cxl_commands(cxlds, exclusive_cmds);
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rc = devm_add_action_or_reset(dev, clear_exclusive, cxlds);
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2021-09-15 03:03:04 +08:00
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if (rc)
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2021-06-16 07:36:31 +08:00
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goto out;
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set_bit(NDD_LABELING, &flags);
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2021-09-10 06:08:15 +08:00
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set_bit(ND_CMD_GET_CONFIG_SIZE, &cmd_mask);
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set_bit(ND_CMD_GET_CONFIG_DATA, &cmd_mask);
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set_bit(ND_CMD_SET_CONFIG_DATA, &cmd_mask);
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nvdimm = nvdimm_create(cxl_nvb->nvdimm_bus, cxl_nvd, NULL, flags,
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cmd_mask, 0, NULL);
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2021-09-15 03:03:04 +08:00
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if (!nvdimm) {
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rc = -ENOMEM;
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2021-06-16 07:36:31 +08:00
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goto out;
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2021-09-15 03:03:04 +08:00
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}
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2021-06-16 07:36:31 +08:00
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2021-09-15 03:03:04 +08:00
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dev_set_drvdata(dev, nvdimm);
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2021-06-16 07:36:31 +08:00
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rc = devm_add_action_or_reset(dev, unregister_nvdimm, nvdimm);
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out:
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device_unlock(&cxl_nvb->dev);
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put_device(&cxl_nvb->dev);
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return rc;
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}
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static struct cxl_driver cxl_nvdimm_driver = {
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.name = "cxl_nvdimm",
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.probe = cxl_nvdimm_probe,
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.id = CXL_DEVICE_NVDIMM,
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};
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2021-11-03 04:29:01 +08:00
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static int cxl_pmem_get_config_size(struct cxl_dev_state *cxlds,
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2021-09-10 06:08:15 +08:00
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struct nd_cmd_get_config_size *cmd,
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unsigned int buf_len)
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{
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if (sizeof(*cmd) > buf_len)
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return -EINVAL;
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*cmd = (struct nd_cmd_get_config_size) {
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2021-11-03 04:29:01 +08:00
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.config_size = cxlds->lsa_size,
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.max_xfer = cxlds->payload_size,
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2021-09-10 06:08:15 +08:00
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};
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return 0;
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}
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2021-11-03 04:29:01 +08:00
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static int cxl_pmem_get_config_data(struct cxl_dev_state *cxlds,
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2021-09-10 06:08:15 +08:00
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struct nd_cmd_get_config_data_hdr *cmd,
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unsigned int buf_len)
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{
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2021-09-09 13:13:15 +08:00
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struct cxl_mbox_get_lsa get_lsa;
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2021-09-10 06:08:15 +08:00
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int rc;
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if (sizeof(*cmd) > buf_len)
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return -EINVAL;
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if (struct_size(cmd, out_buf, cmd->in_length) > buf_len)
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return -EINVAL;
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get_lsa = (struct cxl_mbox_get_lsa) {
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.offset = cmd->in_offset,
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.length = cmd->in_length,
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};
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2021-11-03 04:29:01 +08:00
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rc = cxl_mbox_send_cmd(cxlds, CXL_MBOX_OP_GET_LSA, &get_lsa,
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sizeof(get_lsa), cmd->out_buf, cmd->in_length);
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2021-09-10 06:08:15 +08:00
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cmd->status = 0;
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return rc;
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}
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2021-11-03 04:29:01 +08:00
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static int cxl_pmem_set_config_data(struct cxl_dev_state *cxlds,
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2021-09-10 06:08:15 +08:00
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struct nd_cmd_set_config_hdr *cmd,
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unsigned int buf_len)
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{
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2021-09-09 13:13:15 +08:00
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struct cxl_mbox_set_lsa *set_lsa;
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2021-09-10 06:08:15 +08:00
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int rc;
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if (sizeof(*cmd) > buf_len)
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return -EINVAL;
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/* 4-byte status follows the input data in the payload */
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if (struct_size(cmd, in_buf, cmd->in_length) + 4 > buf_len)
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return -EINVAL;
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set_lsa =
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kvzalloc(struct_size(set_lsa, data, cmd->in_length), GFP_KERNEL);
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if (!set_lsa)
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return -ENOMEM;
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*set_lsa = (struct cxl_mbox_set_lsa) {
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.offset = cmd->in_offset,
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};
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memcpy(set_lsa->data, cmd->in_buf, cmd->in_length);
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2021-11-03 04:29:01 +08:00
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rc = cxl_mbox_send_cmd(cxlds, CXL_MBOX_OP_SET_LSA, set_lsa,
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struct_size(set_lsa, data, cmd->in_length),
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NULL, 0);
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2021-09-10 06:08:15 +08:00
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/*
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* Set "firmware" status (4-packed bytes at the end of the input
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* payload.
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*/
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put_unaligned(0, (u32 *) &cmd->in_buf[cmd->in_length]);
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kvfree(set_lsa);
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return rc;
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}
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static int cxl_pmem_nvdimm_ctl(struct nvdimm *nvdimm, unsigned int cmd,
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void *buf, unsigned int buf_len)
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{
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struct cxl_nvdimm *cxl_nvd = nvdimm_provider_data(nvdimm);
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unsigned long cmd_mask = nvdimm_cmd_mask(nvdimm);
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struct cxl_memdev *cxlmd = cxl_nvd->cxlmd;
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2021-11-03 04:29:01 +08:00
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struct cxl_dev_state *cxlds = cxlmd->cxlds;
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2021-09-10 06:08:15 +08:00
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if (!test_bit(cmd, &cmd_mask))
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return -ENOTTY;
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switch (cmd) {
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case ND_CMD_GET_CONFIG_SIZE:
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2021-11-03 04:29:01 +08:00
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return cxl_pmem_get_config_size(cxlds, buf, buf_len);
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2021-09-10 06:08:15 +08:00
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case ND_CMD_GET_CONFIG_DATA:
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2021-11-03 04:29:01 +08:00
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return cxl_pmem_get_config_data(cxlds, buf, buf_len);
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2021-09-10 06:08:15 +08:00
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case ND_CMD_SET_CONFIG_DATA:
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2021-11-03 04:29:01 +08:00
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return cxl_pmem_set_config_data(cxlds, buf, buf_len);
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2021-09-10 06:08:15 +08:00
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default:
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return -ENOTTY;
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}
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}
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2021-06-16 07:18:17 +08:00
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static int cxl_pmem_ctl(struct nvdimm_bus_descriptor *nd_desc,
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struct nvdimm *nvdimm, unsigned int cmd, void *buf,
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unsigned int buf_len, int *cmd_rc)
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{
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2021-09-10 06:08:15 +08:00
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/*
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* No firmware response to translate, let the transport error
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* code take precedence.
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*/
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*cmd_rc = 0;
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if (!nvdimm)
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return -ENOTTY;
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return cxl_pmem_nvdimm_ctl(nvdimm, cmd, buf, buf_len);
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2021-06-16 07:18:17 +08:00
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}
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static bool online_nvdimm_bus(struct cxl_nvdimm_bridge *cxl_nvb)
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{
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if (cxl_nvb->nvdimm_bus)
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return true;
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cxl_nvb->nvdimm_bus =
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nvdimm_bus_register(&cxl_nvb->dev, &cxl_nvb->nd_desc);
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return cxl_nvb->nvdimm_bus != NULL;
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}
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2021-06-16 07:36:31 +08:00
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static int cxl_nvdimm_release_driver(struct device *dev, void *data)
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2021-06-16 07:18:17 +08:00
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{
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2021-06-16 07:36:31 +08:00
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if (!is_cxl_nvdimm(dev))
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return 0;
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device_release_driver(dev);
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return 0;
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}
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static void offline_nvdimm_bus(struct nvdimm_bus *nvdimm_bus)
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{
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if (!nvdimm_bus)
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2021-06-16 07:18:17 +08:00
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return;
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2021-06-16 07:36:31 +08:00
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/*
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* Set the state of cxl_nvdimm devices to unbound / idle before
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* nvdimm_bus_unregister() rips the nvdimm objects out from
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* underneath them.
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*/
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bus_for_each_dev(&cxl_bus_type, NULL, NULL, cxl_nvdimm_release_driver);
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nvdimm_bus_unregister(nvdimm_bus);
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2021-06-16 07:18:17 +08:00
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}
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static void cxl_nvb_update_state(struct work_struct *work)
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{
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struct cxl_nvdimm_bridge *cxl_nvb =
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container_of(work, typeof(*cxl_nvb), state_work);
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2021-06-16 07:36:31 +08:00
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struct nvdimm_bus *victim_bus = NULL;
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bool release = false, rescan = false;
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2021-06-16 07:18:17 +08:00
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device_lock(&cxl_nvb->dev);
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switch (cxl_nvb->state) {
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case CXL_NVB_ONLINE:
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if (!online_nvdimm_bus(cxl_nvb)) {
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dev_err(&cxl_nvb->dev,
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"failed to establish nvdimm bus\n");
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release = true;
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2021-06-16 07:36:31 +08:00
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} else
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rescan = true;
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2021-06-16 07:18:17 +08:00
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break;
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case CXL_NVB_OFFLINE:
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case CXL_NVB_DEAD:
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2021-06-16 07:36:31 +08:00
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victim_bus = cxl_nvb->nvdimm_bus;
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cxl_nvb->nvdimm_bus = NULL;
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2021-06-16 07:18:17 +08:00
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break;
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default:
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break;
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}
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device_unlock(&cxl_nvb->dev);
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if (release)
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device_release_driver(&cxl_nvb->dev);
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2021-06-16 07:36:31 +08:00
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if (rescan) {
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int rc = bus_rescan_devices(&cxl_bus_type);
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dev_dbg(&cxl_nvb->dev, "rescan: %d\n", rc);
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}
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offline_nvdimm_bus(victim_bus);
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2021-06-16 07:18:17 +08:00
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put_device(&cxl_nvb->dev);
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}
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2021-10-30 03:55:47 +08:00
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static void cxl_nvdimm_bridge_state_work(struct cxl_nvdimm_bridge *cxl_nvb)
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{
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/*
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* Take a reference that the workqueue will drop if new work
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* gets queued.
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*/
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get_device(&cxl_nvb->dev);
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if (!queue_work(cxl_pmem_wq, &cxl_nvb->state_work))
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put_device(&cxl_nvb->dev);
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}
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2021-06-16 07:18:17 +08:00
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static void cxl_nvdimm_bridge_remove(struct device *dev)
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{
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struct cxl_nvdimm_bridge *cxl_nvb = to_cxl_nvdimm_bridge(dev);
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if (cxl_nvb->state == CXL_NVB_ONLINE)
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cxl_nvb->state = CXL_NVB_OFFLINE;
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2021-10-30 03:55:47 +08:00
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cxl_nvdimm_bridge_state_work(cxl_nvb);
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2021-06-16 07:18:17 +08:00
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}
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static int cxl_nvdimm_bridge_probe(struct device *dev)
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{
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struct cxl_nvdimm_bridge *cxl_nvb = to_cxl_nvdimm_bridge(dev);
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if (cxl_nvb->state == CXL_NVB_DEAD)
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return -ENXIO;
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if (cxl_nvb->state == CXL_NVB_NEW) {
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cxl_nvb->nd_desc = (struct nvdimm_bus_descriptor) {
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.provider_name = "CXL",
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.module = THIS_MODULE,
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.ndctl = cxl_pmem_ctl,
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};
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INIT_WORK(&cxl_nvb->state_work, cxl_nvb_update_state);
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|
|
|
}
|
|
|
|
|
|
|
|
cxl_nvb->state = CXL_NVB_ONLINE;
|
2021-10-30 03:55:47 +08:00
|
|
|
cxl_nvdimm_bridge_state_work(cxl_nvb);
|
2021-06-16 07:18:17 +08:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct cxl_driver cxl_nvdimm_bridge_driver = {
|
|
|
|
.name = "cxl_nvdimm_bridge",
|
|
|
|
.probe = cxl_nvdimm_bridge_probe,
|
|
|
|
.remove = cxl_nvdimm_bridge_remove,
|
|
|
|
.id = CXL_DEVICE_NVDIMM_BRIDGE,
|
|
|
|
};
|
|
|
|
|
2021-11-12 02:19:05 +08:00
|
|
|
/*
|
|
|
|
* Return all bridges to the CXL_NVB_NEW state to invalidate any
|
|
|
|
* ->state_work referring to the now destroyed cxl_pmem_wq.
|
|
|
|
*/
|
|
|
|
static int cxl_nvdimm_bridge_reset(struct device *dev, void *data)
|
|
|
|
{
|
|
|
|
struct cxl_nvdimm_bridge *cxl_nvb;
|
|
|
|
|
|
|
|
if (!is_cxl_nvdimm_bridge(dev))
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
cxl_nvb = to_cxl_nvdimm_bridge(dev);
|
|
|
|
device_lock(dev);
|
|
|
|
cxl_nvb->state = CXL_NVB_NEW;
|
|
|
|
device_unlock(dev);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void destroy_cxl_pmem_wq(void)
|
|
|
|
{
|
|
|
|
destroy_workqueue(cxl_pmem_wq);
|
|
|
|
bus_for_each_dev(&cxl_bus_type, NULL, NULL, cxl_nvdimm_bridge_reset);
|
|
|
|
}
|
|
|
|
|
2021-06-16 07:18:17 +08:00
|
|
|
static __init int cxl_pmem_init(void)
|
|
|
|
{
|
|
|
|
int rc;
|
|
|
|
|
2021-09-15 03:03:04 +08:00
|
|
|
set_bit(CXL_MEM_COMMAND_ID_SET_PARTITION_INFO, exclusive_cmds);
|
|
|
|
set_bit(CXL_MEM_COMMAND_ID_SET_SHUTDOWN_STATE, exclusive_cmds);
|
|
|
|
set_bit(CXL_MEM_COMMAND_ID_SET_LSA, exclusive_cmds);
|
|
|
|
|
2021-06-16 07:18:17 +08:00
|
|
|
cxl_pmem_wq = alloc_ordered_workqueue("cxl_pmem", 0);
|
|
|
|
if (!cxl_pmem_wq)
|
|
|
|
return -ENXIO;
|
|
|
|
|
|
|
|
rc = cxl_driver_register(&cxl_nvdimm_bridge_driver);
|
|
|
|
if (rc)
|
2021-06-16 07:36:31 +08:00
|
|
|
goto err_bridge;
|
|
|
|
|
|
|
|
rc = cxl_driver_register(&cxl_nvdimm_driver);
|
|
|
|
if (rc)
|
|
|
|
goto err_nvdimm;
|
2021-06-16 07:18:17 +08:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
2021-06-16 07:36:31 +08:00
|
|
|
err_nvdimm:
|
|
|
|
cxl_driver_unregister(&cxl_nvdimm_bridge_driver);
|
|
|
|
err_bridge:
|
2021-11-12 02:19:05 +08:00
|
|
|
destroy_cxl_pmem_wq();
|
2021-06-16 07:18:17 +08:00
|
|
|
return rc;
|
|
|
|
}
|
|
|
|
|
|
|
|
static __exit void cxl_pmem_exit(void)
|
|
|
|
{
|
2021-06-16 07:36:31 +08:00
|
|
|
cxl_driver_unregister(&cxl_nvdimm_driver);
|
2021-06-16 07:18:17 +08:00
|
|
|
cxl_driver_unregister(&cxl_nvdimm_bridge_driver);
|
2021-11-12 02:19:05 +08:00
|
|
|
destroy_cxl_pmem_wq();
|
2021-06-16 07:18:17 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
MODULE_LICENSE("GPL v2");
|
|
|
|
module_init(cxl_pmem_init);
|
|
|
|
module_exit(cxl_pmem_exit);
|
|
|
|
MODULE_IMPORT_NS(CXL);
|
|
|
|
MODULE_ALIAS_CXL(CXL_DEVICE_NVDIMM_BRIDGE);
|
2021-06-16 07:36:31 +08:00
|
|
|
MODULE_ALIAS_CXL(CXL_DEVICE_NVDIMM);
|