49 lines
1.5 KiB
C
49 lines
1.5 KiB
C
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/*
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* include/asm-v850/v850e_cache.h -- Cache control for V850E cache memories
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*
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* Copyright (C) 2001,03 NEC Electronics Corporation
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* Copyright (C) 2001,03 Miles Bader <miles@gnu.org>
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*
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* This file is subject to the terms and conditions of the GNU General
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* Public License. See the file COPYING in the main directory of this
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* archive for more details.
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*
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* Written by Miles Bader <miles@gnu.org>
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*/
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/* This file implements cache control for the rather simple cache used on
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some V850E CPUs, specifically the NB85E/TEG CPU-core and the V850E/ME2
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CPU. V850E2 processors have their own (better) cache
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implementation. */
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#ifndef __V850_V850E_CACHE_H__
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#define __V850_V850E_CACHE_H__
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#include <asm/types.h>
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/* Cache control registers. */
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#define V850E_CACHE_BHC_ADDR 0xFFFFF06A
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#define V850E_CACHE_BHC (*(volatile u16 *)V850E_CACHE_BHC_ADDR)
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#define V850E_CACHE_ICC_ADDR 0xFFFFF070
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#define V850E_CACHE_ICC (*(volatile u16 *)V850E_CACHE_ICC_ADDR)
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#define V850E_CACHE_ISI_ADDR 0xFFFFF072
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#define V850E_CACHE_ISI (*(volatile u16 *)V850E_CACHE_ISI_ADDR)
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#define V850E_CACHE_DCC_ADDR 0xFFFFF078
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#define V850E_CACHE_DCC (*(volatile u16 *)V850E_CACHE_DCC_ADDR)
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/* Size of a cache line in bytes. */
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#define V850E_CACHE_LINE_SIZE 16
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/* For <asm/cache.h> */
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#define L1_CACHE_BYTES V850E_CACHE_LINE_SIZE
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#if defined(__KERNEL__) && !defined(__ASSEMBLY__)
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/* Set caching params via the BHC, ICC, and DCC registers. */
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void v850e_cache_enable (u16 bhc, u16 icc, u16 dcc);
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#endif /* __KERNEL__ && !__ASSEMBLY__ */
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#endif /* __V850_V850E_CACHE_H__ */
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