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platform/x86: intel_pmc_core: export platform global reset bits via etr3 sysfs file During PCH (platform/board) manufacturing process a global platform reset has to be induced in order for the configuration changes take the effect upon following platform reset. This is an internal platform state and is not intended to be used in the regular platform resets. The setting is exposed via ETR3 (Extended Test Mode Register 3). After the manufacturing process is completed the register cannot be written anymore and is hardware locked. This setting was commonly done by accessing PMC registers via /dev/mem but due to security concerns /dev/mem access is much more restricted, hence the reason for exposing this setting via the dedicated sysfs interface. To prevent post manufacturing abuse the register is protected by hardware locking and the file is set to read-only mode via is_visible handler. The register in MMIO space is defined for Cannon Lake and newer PCHs. Cc: Hans de Goede <hdegoede@redhat.com> Cc: David E Box <david.e.box@intel.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Tamar Mashiah <tamar.mashiah@intel.com> Signed-off-by: Tomas Winkler <tomas.winkler@intel.com> Link: https://lore.kernel.org/r/20210411141532.3004893-1-tomas.winkler@intel.com Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2021-04-11 22:15:32 +08:00
What: /sys/devices/platform/<platform>/etr3
Date: Apr 2021
KernelVersion: 5.13
Contact: "Tomas Winkler" <tomas.winkler@intel.com>
Description:
The file exposes "Extended Test Mode Register 3" global
reset bits. The bits are used during an Intel platform
manufacturing process to indicate that consequent reset
of the platform is a "global reset". This type of reset
is required in order for manufacturing configurations
to take effect.
Display global reset setting bits for PMC.
ABI: sysfs-platform-intel-pmc: add blank lines to make it valid for ReST The ReST format requires blank lines before/after identation changes, for it to properly detect lists. Fixes: ee7abc105e2b ("platform/x86: intel_pmc_core: export platform global reset bits via etr3 sysfs file") Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org> Link: https://lore.kernel.org/r/3673e1a255ad4100c933af215b60d68ba126f820.1632740376.git.mchehab+huawei@kernel.org Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2021-09-27 19:10:56 +08:00
platform/x86: intel_pmc_core: export platform global reset bits via etr3 sysfs file During PCH (platform/board) manufacturing process a global platform reset has to be induced in order for the configuration changes take the effect upon following platform reset. This is an internal platform state and is not intended to be used in the regular platform resets. The setting is exposed via ETR3 (Extended Test Mode Register 3). After the manufacturing process is completed the register cannot be written anymore and is hardware locked. This setting was commonly done by accessing PMC registers via /dev/mem but due to security concerns /dev/mem access is much more restricted, hence the reason for exposing this setting via the dedicated sysfs interface. To prevent post manufacturing abuse the register is protected by hardware locking and the file is set to read-only mode via is_visible handler. The register in MMIO space is defined for Cannon Lake and newer PCHs. Cc: Hans de Goede <hdegoede@redhat.com> Cc: David E Box <david.e.box@intel.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Tamar Mashiah <tamar.mashiah@intel.com> Signed-off-by: Tomas Winkler <tomas.winkler@intel.com> Link: https://lore.kernel.org/r/20210411141532.3004893-1-tomas.winkler@intel.com Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2021-04-11 22:15:32 +08:00
* bit 31 - global reset is locked
* bit 20 - global reset is set
ABI: sysfs-platform-intel-pmc: add blank lines to make it valid for ReST The ReST format requires blank lines before/after identation changes, for it to properly detect lists. Fixes: ee7abc105e2b ("platform/x86: intel_pmc_core: export platform global reset bits via etr3 sysfs file") Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org> Link: https://lore.kernel.org/r/3673e1a255ad4100c933af215b60d68ba126f820.1632740376.git.mchehab+huawei@kernel.org Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2021-09-27 19:10:56 +08:00
platform/x86: intel_pmc_core: export platform global reset bits via etr3 sysfs file During PCH (platform/board) manufacturing process a global platform reset has to be induced in order for the configuration changes take the effect upon following platform reset. This is an internal platform state and is not intended to be used in the regular platform resets. The setting is exposed via ETR3 (Extended Test Mode Register 3). After the manufacturing process is completed the register cannot be written anymore and is hardware locked. This setting was commonly done by accessing PMC registers via /dev/mem but due to security concerns /dev/mem access is much more restricted, hence the reason for exposing this setting via the dedicated sysfs interface. To prevent post manufacturing abuse the register is protected by hardware locking and the file is set to read-only mode via is_visible handler. The register in MMIO space is defined for Cannon Lake and newer PCHs. Cc: Hans de Goede <hdegoede@redhat.com> Cc: David E Box <david.e.box@intel.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Tamar Mashiah <tamar.mashiah@intel.com> Signed-off-by: Tomas Winkler <tomas.winkler@intel.com> Link: https://lore.kernel.org/r/20210411141532.3004893-1-tomas.winkler@intel.com Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2021-04-11 22:15:32 +08:00
Writing bit 20 value to the etr3 will induce
a platform "global reset" upon consequent platform reset,
in case the register is not locked.
The "global reset bit" should be locked on a production
system and the file is in read-only mode.