158 lines
5.0 KiB
C
158 lines
5.0 KiB
C
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/*
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* header file specific for ddb5476
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*
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* Copyright (C) 2001 MontaVista Software Inc.
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* Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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*/
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/*
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* Memory map (physical address)
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*
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* Note most of the following address must be properly aligned by the
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* corresponding size. For example, if PCI_IO_SIZE is 16MB, then
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* PCI_IO_BASE must be aligned along 16MB boundary.
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*/
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#define DDB_SDRAM_BASE 0x00000000
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#define DDB_SDRAM_SIZE 0x04000000 /* 64MB */
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#define DDB_DCS3_BASE 0x04000000 /* flash 1 */
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#define DDB_DCS3_SIZE 0x01000000 /* 16MB */
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#define DDB_DCS2_BASE 0x05000000 /* flash 2 */
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#define DDB_DCS2_SIZE 0x01000000 /* 16MB */
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#define DDB_PCI_IO_BASE 0x06000000
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#define DDB_PCI_IO_SIZE 0x02000000 /* 32 MB */
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#define DDB_PCI_MEM_BASE 0x08000000
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#define DDB_PCI_MEM_SIZE 0x08000000 /* 128 MB */
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#define DDB_DCS5_BASE 0x13000000 /* DDB status regs */
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#define DDB_DCS5_SIZE 0x00200000 /* 2MB, 8-bit */
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#define DDB_DCS4_BASE 0x14000000 /* DDB control regs */
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#define DDB_DCS4_SIZE 0x00200000 /* 2MB, 8-bit */
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#define DDB_INTCS_BASE 0x1fa00000 /* VRC5476 control regs */
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#define DDB_INTCS_SIZE 0x00200000 /* 2MB */
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#define DDB_BOOTCS_BASE 0x1fc00000 /* Boot ROM / EPROM /Flash */
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#define DDB_BOOTCS_SIZE 0x00200000 /* 2 MB - doc says 4MB */
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/* aliases */
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#define DDB_PCI_CONFIG_BASE DDB_PCI_MEM_BASE
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#define DDB_PCI_CONFIG_SIZE DDB_PCI_MEM_SIZE
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/* PCI intr ack share PCIW0 with PCI IO */
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#define DDB_PCI_IACK_BASE DDB_PCI_IO_BASE
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/*
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* Interrupt mapping
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*
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* We have three interrupt controllers:
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*
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* . CPU itself - 8 sources
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* . i8259 - 16 sources
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* . vrc5476 - 16 sources
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*
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* They connected as follows:
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* all vrc5476 interrupts are routed to cpu IP2 (by software setting)
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* all i2869 are routed to INTC in vrc5476 (by hardware connection)
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*
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* All VRC5476 PCI interrupts are level-triggered (no ack needed).
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* All PCI irq but INTC are active low.
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*/
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/*
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* irq number block assignment
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*/
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#define NUM_CPU_IRQ 8
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#define NUM_I8259_IRQ 16
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#define NUM_VRC5476_IRQ 16
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#define DDB_IRQ_BASE 0
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#define I8259_IRQ_BASE DDB_IRQ_BASE
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#define VRC5476_IRQ_BASE (I8259_IRQ_BASE + NUM_I8259_IRQ)
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#define CPU_IRQ_BASE (VRC5476_IRQ_BASE + NUM_VRC5476_IRQ)
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/*
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* vrc5476 irq defs, see page 52-64 of Vrc5074 system controller manual
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*/
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#define VRC5476_IRQ_CPCE 0 /* cpu parity error */
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#define VRC5476_IRQ_CNTD 1 /* cpu no target */
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#define VRC5476_IRQ_MCE 2 /* memory check error */
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#define VRC5476_IRQ_DMA 3 /* DMA */
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#define VRC5476_IRQ_UART 4 /* vrc5476 builtin UART, not used */
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#define VRC5476_IRQ_WDOG 5 /* watchdog timer */
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#define VRC5476_IRQ_GPT 6 /* general purpose timer */
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#define VRC5476_IRQ_LBRT 7 /* local bus read timeout */
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#define VRC5476_IRQ_INTA 8 /* PCI INT #A */
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#define VRC5476_IRQ_INTB 9 /* PCI INT #B */
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#define VRC5476_IRQ_INTC 10 /* PCI INT #C */
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#define VRC5476_IRQ_INTD 11 /* PCI INT #D */
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#define VRC5476_IRQ_INTE 12 /* PCI INT #E */
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#define VRC5476_IRQ_RESERVED_13 13 /* reserved */
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#define VRC5476_IRQ_PCIS 14 /* PCI SERR # */
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#define VRC5476_IRQ_PCI 15 /* PCI internal error */
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/*
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* i2859 irq assignment
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*/
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#define I8259_IRQ_RESERVED_0 0
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#define I8259_IRQ_KEYBOARD 1 /* M1543 default */
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#define I8259_IRQ_CASCADE 2
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#define I8259_IRQ_UART_B 3 /* M1543 default, may conflict with RTC according to schematic diagram */
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#define I8259_IRQ_UART_A 4 /* M1543 default */
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#define I8259_IRQ_PARALLEL 5 /* M1543 default */
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#define I8259_IRQ_RESERVED_6 6
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#define I8259_IRQ_RESERVED_7 7
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#define I8259_IRQ_RTC 8 /* who set this? */
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#define I8259_IRQ_USB 9 /* ddb_setup */
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#define I8259_IRQ_PMU 10 /* ddb_setup */
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#define I8259_IRQ_RESERVED_11 11
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#define I8259_IRQ_RESERVED_12 12 /* m1543_irq_setup */
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#define I8259_IRQ_RESERVED_13 13
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#define I8259_IRQ_HDC1 14 /* default and ddb_setup */
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#define I8259_IRQ_HDC2 15 /* default */
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/*
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* misc
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*/
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#define VRC5476_I8259_CASCADE VRC5476_IRQ_INTC
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#define CPU_VRC5476_CASCADE 2
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#define is_i8259_irq(irq) ((irq) < NUM_I8259_IRQ)
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#define nile4_to_irq(n) ((n)+NUM_I8259_IRQ)
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#define irq_to_nile4(n) ((n)-NUM_I8259_IRQ)
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/*
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* low-level irq functions
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*/
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#ifndef __ASSEMBLY__
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extern void nile4_map_irq(int nile4_irq, int cpu_irq);
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extern void nile4_map_irq_all(int cpu_irq);
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extern void nile4_enable_irq(int nile4_irq);
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extern void nile4_disable_irq(int nile4_irq);
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extern void nile4_disable_irq_all(void);
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extern u16 nile4_get_irq_stat(int cpu_irq);
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extern void nile4_enable_irq_output(int cpu_irq);
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extern void nile4_disable_irq_output(int cpu_irq);
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extern void nile4_set_pci_irq_polarity(int pci_irq, int high);
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extern void nile4_set_pci_irq_level_or_edge(int pci_irq, int level);
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extern void nile4_clear_irq(int nile4_irq);
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extern void nile4_clear_irq_mask(u32 mask);
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extern u8 nile4_i8259_iack(void);
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extern void nile4_dump_irq_status(void); /* Debug */
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#endif /* !__ASSEMBLY__ */
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