129 lines
3.9 KiB
C
129 lines
3.9 KiB
C
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/*
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* include/asm-v850/rte_ma1_cb.h -- Midas labs RTE-V850/MA1-CB board
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*
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* Copyright (C) 2001,02,03 NEC Electronics Corporation
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* Copyright (C) 2001,02,03 Miles Bader <miles@gnu.org>
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*
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* This file is subject to the terms and conditions of the GNU General
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* Public License. See the file COPYING in the main directory of this
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* archive for more details.
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*
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* Written by Miles Bader <miles@gnu.org>
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*/
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#ifndef __V850_RTE_MA1_CB_H__
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#define __V850_RTE_MA1_CB_H__
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#include <asm/rte_cb.h> /* Common defs for Midas RTE-CB boards. */
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#define PLATFORM "rte-v850e/ma1-cb"
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#define PLATFORM_LONG "Midas lab RTE-V850E/MA1-CB"
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#define CPU_CLOCK_FREQ 50000000 /* 50MHz */
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/* 1MB of onboard SRAM. Note that the monitor ROM uses parts of this
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for its own purposes, so care must be taken. Some address lines are
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not decoded, so the SRAM area is mirrored every 1MB from 0x400000 to
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0x800000 (exclusive). */
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#define SRAM_ADDR 0x00400000
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#define SRAM_SIZE 0x00100000 /* 1MB */
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/* 32MB of onbard SDRAM. */
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#define SDRAM_ADDR 0x00800000
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#define SDRAM_SIZE 0x02000000 /* 32MB */
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/* CPU addresses of GBUS memory spaces. */
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#define GCS0_ADDR 0x05000000 /* GCS0 - Common SRAM (2MB) */
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#define GCS0_SIZE 0x00200000 /* 2MB */
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#define GCS1_ADDR 0x06000000 /* GCS1 - Flash ROM (8MB) */
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#define GCS1_SIZE 0x00800000 /* 8MB */
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#define GCS2_ADDR 0x07900000 /* GCS2 - I/O registers */
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#define GCS2_SIZE 0x00400000 /* 4MB */
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#define GCS5_ADDR 0x04000000 /* GCS5 - PCI bus space */
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#define GCS5_SIZE 0x01000000 /* 16MB */
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#define GCS6_ADDR 0x07980000 /* GCS6 - PCI control registers */
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#define GCS6_SIZE 0x00000200 /* 512B */
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/* For <asm/page.h> */
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#define PAGE_OFFSET SRAM_ADDR
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/* The GBUS GINT0 - GINT3 interrupts are connected to the INTP000 - INTP011
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pins on the CPU. These are shared among the GBUS interrupts. */
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#define IRQ_GINT(n) IRQ_INTP(n)
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#define IRQ_GINT_NUM 4
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/* Used by <asm/rte_cb.h> to derive NUM_MACH_IRQS. */
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#define NUM_RTE_CB_IRQS NUM_CPU_IRQS
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#ifdef CONFIG_ROM_KERNEL
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/* Kernel is in ROM, starting at address 0. */
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#define INTV_BASE 0
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#else /* !CONFIG_ROM_KERNEL */
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#ifdef CONFIG_RTE_CB_MULTI
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/* Using RAM kernel with ROM monitor for Multi debugger. */
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/* The chip's real interrupt vectors are in ROM, but they jump to a
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secondary interrupt vector table in RAM. */
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#define INTV_BASE 0x004F8000
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/* Scratch memory used by the ROM monitor, which shouldn't be used by
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linux (except for the alternate interrupt vector area, defined
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above). */
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#define MON_SCRATCH_ADDR 0x004F8000
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#define MON_SCRATCH_SIZE 0x00008000 /* 32KB */
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#else /* !CONFIG_RTE_CB_MULTI */
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/* Using RAM-kernel. Assume some sort of boot-loader got us loaded at
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address 0. */
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#define INTV_BASE 0
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#endif /* CONFIG_RTE_CB_MULTI */
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#endif /* CONFIG_ROM_KERNEL */
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/* Some misc. on-board devices. */
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/* Seven-segment LED display (two digits). Write-only. */
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#define LED_ADDR(n) (0x07802000 + (n))
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#define LED(n) (*(volatile unsigned char *)LED_ADDR(n))
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#define LED_NUM_DIGITS 2
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/* Override the basic MA uart pre-initialization so that we can
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initialize extra stuff. */
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#undef V850E_UART_PRE_CONFIGURE /* should be defined by <asm/ma.h> */
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#define V850E_UART_PRE_CONFIGURE rte_ma1_cb_uart_pre_configure
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#ifndef __ASSEMBLY__
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extern void rte_ma1_cb_uart_pre_configure (unsigned chan,
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unsigned cflags, unsigned baud);
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#endif
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/* This board supports RTS/CTS for the on-chip UART, but only for channel 0. */
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/* CTS for UART channel 0 is pin P43 (bit 3 of port 4). */
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#define V850E_UART_CTS(chan) ((chan) == 0 ? !(MA_PORT4_IO & 0x8) : 1)
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/* RTS for UART channel 0 is pin P42 (bit 2 of port 4). */
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#define V850E_UART_SET_RTS(chan, val) \
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do { \
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if (chan == 0) { \
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unsigned old = MA_PORT4_IO; \
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if (val) \
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MA_PORT4_IO = old & ~0x4; \
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else \
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MA_PORT4_IO = old | 0x4; \
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} \
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} while (0)
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#endif /* __V850_RTE_MA1_CB_H__ */
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