86 lines
3.8 KiB
C
86 lines
3.8 KiB
C
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#ifndef _INCLUDE_ASM_ARCH_REGS_CLKCTRL_H
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#define _INCLUDE_ASM_ARCH_REGS_CLKCTRL_H
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#include <mach/stmp3xxx_regs.h>
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#define REGS_CLKCTRL_BASE (REGS_BASE + 0x00040000)
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#define HW_CLKCTRL_PLLCTRL0_ADDR (REGS_CLKCTRL_BASE + 0x00)
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HW_REGISTER(HW_CLKCTRL_PLLCTRL0, REGS_CLKCTRL_BASE, 0x00)
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#define BM_CLKCTRL_PLLCTRL0_EN_USB_CLKS 0x00040000
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#define HW_CLKCTRL_PLLCTRL1_ADDR (REGS_CLKCTRL_BASE + 0x10)
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HW_REGISTER(HW_CLKCTRL_PLLCTRL1, REGS_CLKCTRL_BASE, 0x10)
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#define HW_CLKCTRL_CPU_ADDR (REGS_CLKCTRL_BASE + 0x20)
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HW_REGISTER(HW_CLKCTRL_CPU, REGS_CLKCTRL_BASE, 0x20)
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#define BM_CLKCTRL_CPU_DIV_CPU 0x0000003F
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#define BF_CLKCTRL_CPU_DIV_CPU(v) \
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(((v) << 0) & BM_CLKCTRL_CPU_DIV_CPU)
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#define HW_CLKCTRL_HBUS_ADDR (REGS_CLKCTRL_BASE + 0x30)
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HW_REGISTER(HW_CLKCTRL_HBUS, REGS_CLKCTRL_BASE, 0x30)
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#define BM_CLKCTRL_HBUS_DIV_FRAC_EN 0 /* for compatitibility */
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#define BM_CLKCTRL_HBUS_DIV 0x0000001F
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#define BF_CLKCTRL_HBUS_DIV(v) \
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(((v) << 0) & BM_CLKCTRL_HBUS_DIV)
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#define HW_CLKCTRL_XBUS_ADDR (REGS_CLKCTRL_BASE + 0x40)
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HW_REGISTER(HW_CLKCTRL_XBUS, REGS_CLKCTRL_BASE, 0x40)
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#define HW_CLKCTRL_XTAL_ADDR (REGS_CLKCTRL_BASE + 0x50)
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HW_REGISTER(HW_CLKCTRL_XTAL, REGS_CLKCTRL_BASE, 0x50)
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#define HW_CLKCTRL_PIX_ADDR (REGS_CLKCTRL_BASE + 0x60)
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HW_REGISTER(HW_CLKCTRL_PIX, REGS_CLKCTRL_BASE, 0x60)
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#define BM_CLKCTRL_PIX_CLKGATE 0x80000000
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#define BM_CLKCTRL_PIX_BUSY 0x20000000
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#define BM_CLKCTRL_PIX_DIV 0x00007FFF
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#define BP_CLKCTRL_PIX_DIV 0
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#define BF_CLKCTRL_PIX_DIV(v) \
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(((v) << BP_CLKCTRL_PIX_DIV) & BM_CLKCTRL_PIX_DIV)
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#define HW_CLKCTRL_SSP_ADDR (REGS_CLKCTRL_BASE + 0x70)
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HW_REGISTER(HW_CLKCTRL_SSP, REGS_CLKCTRL_BASE, 0x70)
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#define HW_CLKCTRL_GPMI_ADDR (REGS_CLKCTRL_BASE + 0x80)
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HW_REGISTER(HW_CLKCTRL_GPMI, REGS_CLKCTRL_BASE, 0x80)
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#define HW_CLKCTRL_SPDIF_ADDR (REGS_CLKCTRL_BASE + 0x90)
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HW_REGISTER(HW_CLKCTRL_SPDIF, REGS_CLKCTRL_BASE, 0x90)
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#define HW_CLKCTRL_EMI_ADDR (REGS_CLKCTRL_BASE + 0xA0)
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HW_REGISTER(HW_CLKCTRL_EMI, REGS_CLKCTRL_BASE, 0xA0)
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#define HW_CLKCTRL_IR_ADDR (REGS_CLKCTRL_BASE + 0xB0)
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HW_REGISTER(HW_CLKCTRL_IR, REGS_CLKCTRL_BASE, 0xB0)
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#define HW_CLKCTRL_SAIF_ADDR (REGS_CLKCTRL_BASE + 0xC0)
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HW_REGISTER(HW_CLKCTRL_SAIF, REGS_CLKCTRL_BASE, 0xC0)
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#define HW_CLKCTRL_FRAC_ADDR (REGS_CLKCTRL_BASE + 0xD0)
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HW_REGISTER(HW_CLKCTRL_FRAC, REGS_CLKCTRL_BASE, 0xD0)
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#define BM_CLKCTRL_FRAC_CLKGATEIO 0x80000000
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#define BM_CLKCTRL_FRAC_IO_STABLE 0x40000000
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#define BM_CLKCTRL_FRAC_IOFRAC 0x3F000000
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#define BP_CLKCTRL_FRAC_IOFRAC 24
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#define BF_CLKCTRL_FRAC_IOFRAC(v) \
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(((v) << BP_CLKCTRL_FRAC_IOFRAC) & BM_CLKCTRL_FRAC_IOFRAC)
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#define BM_CLKCTRL_FRAC_CLKGATEPIX 0x00800000
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#define BM_CLKCTRL_FRAC_PIXFRAC 0x003F0000
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#define BP_CLKCTRL_FRAC_PIXFRAC 16
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#define BF_CLKCTRL_FRAC_PIXFRAC(v) \
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(((v) << BP_CLKCTRL_FRAC_PIXFRAC) & BM_CLKCTRL_FRAC_PIXFRAC)
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#define BM_CLKCTRL_FRAC_CLKGATEEMI 0x00008000
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#define BM_CLKCTRL_FRAC_EMIFRAC 0x00003F00
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#define BP_CLKCTRL_FRAC_EMIFRAC 8
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#define BF_CLKCTRL_FRAC_EMIFRAC(v) \
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(((v) << BP_CLKCTRL_FRAC_EMIFRAC) & BM_CLKCTRL_FRAC_EMIFRAC)
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#define BM_CLKCTRL_FRAC_CLKGATECPU 0x00000080
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#define BM_CLKCTRL_FRAC_CPUFRAC 0x0000003F
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#define BP_CLKCTRL_FRAC_CPUFRAC 0
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#define BF_CLKCTRL_FRAC_CPUFRAC(v) \
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(((v) << BP_CLKCTRL_FRAC_CPUFRAC) & BM_CLKCTRL_FRAC_CPUFRAC)
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#define HW_CLKCTRL_CLKSEQ_ADDR (REGS_CLKCTRL_BASE + 0xE0)
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HW_REGISTER(HW_CLKCTRL_CLKSEQ, REGS_CLKCTRL_BASE, 0xE0)
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#define BM_CLKCTRL_CLKSEQ_BYPASS_CPU 0x00000080
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#define BM_CLKCTRL_CLKSEQ_BYPASS_EMI 0x00000040
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#define BM_CLKCTRL_CLKSEQ_BYPASS_SSP 0x00000020
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#define BM_CLKCTRL_CLKSEQ_BYPASS_GPMI 0x00000010
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#define BM_CLKCTRL_CLKSEQ_BYPASS_IR 0x00000008
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#define BM_CLKCTRL_CLKSEQ_BYPASS_PIX 0x00000002
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#define BM_CLKCTRL_CLKSEQ_BYPASS_SAIF 0x00000001
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HW_REGISTER_WO(HW_CLKCTRL_RESET, REGS_CLKCTRL_BASE, 0xF0)
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#define BM_CLKCTRL_RESET_CHIP 0x00000002
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#define BM_CLKCTRL_RESET_DIG 0x00000001
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#endif /* _INCLUDE_ASM_ARCH_REGS_CLKCTRL_H */
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