2007-06-21 11:34:16 +08:00
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/*
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* File: include/asm-blackfin/mach-bf548/anomaly.h
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* Based on:
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* Author:
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*
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* Created:
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* Description:
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*
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* Rev:
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*
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* Modified:
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*
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*
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* Bugs: Enter bugs at http://blackfin.uclinux.org/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; see the file COPYING.
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* If not, write to the Free Software Foundation,
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* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*/
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#ifndef _MACH_ANOMALY_H_
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#define _MACH_ANOMALY_H_
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#define ANOMALY_05000074 /* A multi issue instruction with dsp32shiftimm in
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slot1 and store of a P register in slot 2 is not
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supported */
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#define ANOMALY_05000119 /* DMA_RUN bit is not valid after a Peripheral Receive
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Channel DMA stops */
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#define ANOMALY_05000122 /* Rx.H can not be used to access 16-bit System MMR
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registers. */
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#define ANOMALY_05000245 /* Spurious Hardware Error from an Access in the
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Shadow of a Conditional Branch */
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#define ANOMALY_05000255 /* Entering Hibernate Mode with RTC Seconds event
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interrupt not functional */
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#define ANOMALY_05000265 /* Sensitivity to noise with slow input edge rates on
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SPORT external receive and transmit clocks. */
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#define ANOMALY_05000272 /* Certain data cache write through modes fail for
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VDDint <=0.9V */
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2007-07-12 22:41:45 +08:00
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#define ANOMALY_05000281 /* False Hardware Error Exception when ISR context is
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not restored */
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2007-06-21 11:34:16 +08:00
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#define ANOMALY_05000310 /* False Hardware Errors Caused by Fetches at the
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Boundary of Reserved Memory */
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#define ANOMALY_05000312 /* Errors When SSYNC, CSYNC, or Loads to LT, LB and
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LC Registers Are Interrupted */
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#define ANOMALY_05000324 /* TWI Slave Boot Mode Is Not Functional */
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#define ANOMALY_05000325 /* External FIFO Boot Mode Is Not Functional */
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#define ANOMALY_05000327 /* Data Lost When Core and DMA Accesses Are Made to
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the USB FIFO Simultaneously */
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#define ANOMALY_05000328 /* Incorrect Access of OTP_STATUS During otp_write()
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function */
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#define ANOMALY_05000329 /* Synchronous Burst Flash Boot Mode Is Not Functional
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*/
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#define ANOMALY_05000330 /* Host DMA Boot Mode Is Not Functional */
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#define ANOMALY_05000334 /* Inadequate Timing Margins on DDR DQS to DQ and DQM
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Skew */
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#define ANOMALY_05000335 /* Inadequate Rotary Debounce Logic Duration */
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#define ANOMALY_05000336 /* Phantom Interrupt Occurs After First Configuration
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of Host DMA Port */
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#define ANOMALY_05000337 /* Disallowed Configuration Prevents Subsequent
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Allowed Configuration on Host DMA Port */
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#define ANOMALY_05000338 /* Slave-Mode SPI0 MISO Failure With CPHA = 0 */
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#endif /* _MACH_ANOMALY_H_ */
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