wifi: rtlwifi: Adjust rtl8192d-common for USB
A few of the shared functions need small changes for the USB driver: - firmware loading - efuse reading - rate mask updating - rf register reading - initial gain for scanning Also, add a few macros to wifi.h and initialise rtlhal.interfaceindex for USB devices. Signed-off-by: Bitterblue Smith <rtl8821cerfe2@gmail.com> Acked-by: Ping-Ke Shih <pkshih@realtek.com> Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Link: https://msgid.link/28100330-f421-4b85-b41b-f1045380cef2@gmail.com
This commit is contained in:
Bitterblue Smith
Ping-Ke Shih
parent
d75589a013
commit
014bba73b5
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@ -1211,7 +1211,7 @@ static u8 efuse_calculate_word_cnts(u8 word_en)
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}
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int rtl_get_hwinfo(struct ieee80211_hw *hw, struct rtl_priv *rtlpriv,
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int max_size, u8 *hwinfo, int *params)
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int max_size, u8 *hwinfo, const int *params)
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{
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struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
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struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
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@ -89,7 +89,7 @@ void efuse_force_write_vendor_id(struct ieee80211_hw *hw);
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void efuse_re_pg_section(struct ieee80211_hw *hw, u8 section_idx);
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void efuse_power_switch(struct ieee80211_hw *hw, u8 write, u8 pwrstate);
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int rtl_get_hwinfo(struct ieee80211_hw *hw, struct rtl_priv *rtlpriv,
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int max_size, u8 *hwinfo, int *params);
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int max_size, u8 *hwinfo, const int *params);
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void rtl_fill_dummy(u8 *pfwbuf, u32 *pfwlen);
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void rtl_fw_page_write(struct ieee80211_hw *hw, u32 page, u8 *buffer,
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u32 size);
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@ -98,24 +98,45 @@ int rtl92d_fw_free_to_go(struct ieee80211_hw *hw)
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}
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EXPORT_SYMBOL_GPL(rtl92d_fw_free_to_go);
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#define RTL_USB_DELAY_FACTOR 60
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void rtl92d_firmware_selfreset(struct ieee80211_hw *hw)
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{
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struct rtl_priv *rtlpriv = rtl_priv(hw);
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struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
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u8 u1b_tmp;
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u8 delay = 100;
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if (rtlhal->interface == INTF_USB) {
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delay *= RTL_USB_DELAY_FACTOR;
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rtl_write_byte(rtlpriv, REG_FSIMR, 0);
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/* We need to disable other HRCV INT to influence 8051 reset. */
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rtl_write_byte(rtlpriv, REG_FWIMR, 0x20);
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/* Close mask to prevent incorrect FW write operation. */
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rtl_write_byte(rtlpriv, REG_FTIMR, 0);
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}
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/* Set (REG_HMETFR + 3) to 0x20 is reset 8051 */
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rtl_write_byte(rtlpriv, REG_HMETFR + 3, 0x20);
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u1b_tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
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while (u1b_tmp & BIT(2)) {
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while (u1b_tmp & (FEN_CPUEN >> 8)) {
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delay--;
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if (delay == 0)
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break;
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udelay(50);
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u1b_tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
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}
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if (rtlhal->interface == INTF_USB) {
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if ((u1b_tmp & (FEN_CPUEN >> 8)) && delay == 0)
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rtl_write_byte(rtlpriv, REG_FWIMR, 0);
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}
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WARN_ONCE((delay <= 0), "rtl8192de: 8051 reset failed!\n");
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rtl_dbg(rtlpriv, COMP_FW, DBG_DMESG,
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"=====> 8051 reset success (%d)\n", delay);
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@ -25,6 +25,16 @@
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#define GET_FIRMWARE_HDR_SUB_VER(__fwhdr) \
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le32_get_bits(*(__le32 *)((__fwhdr) + 4), GENMASK(23, 16))
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#define RAID_MASK GENMASK(31, 28)
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#define RATE_MASK_MASK GENMASK(27, 0)
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#define SHORT_GI_MASK BIT(5)
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#define MACID_MASK GENMASK(4, 0)
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struct rtl92d_rate_mask_h2c {
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__le32 rate_mask_and_raid;
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u8 macid_and_short_gi;
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} __packed;
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bool rtl92d_is_fw_downloaded(struct rtl_priv *rtlpriv);
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void rtl92d_enable_fw_download(struct ieee80211_hw *hw, bool enable);
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void rtl92d_write_fw(struct ieee80211_hw *hw,
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@ -618,9 +618,14 @@ static void _rtl92de_read_macphymode_from_prom(struct ieee80211_hw *hw,
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{
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struct rtl_priv *rtlpriv = rtl_priv(hw);
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struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
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u8 macphy_crvalue = content[EEPROM_MAC_FUNCTION];
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bool is_single_mac = true;
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if (macphy_crvalue & BIT(3)) {
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if (rtlhal->interface == INTF_PCI)
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is_single_mac = !!(content[EEPROM_MAC_FUNCTION] & BIT(3));
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else if (rtlhal->interface == INTF_USB)
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is_single_mac = !(content[EEPROM_ENDPOINT_SETTING] & BIT(0));
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if (is_single_mac) {
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rtlhal->macphymode = SINGLEMAC_SINGLEPHY;
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rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
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"MacPhyMode SINGLEMAC_SINGLEPHY\n");
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@ -659,6 +664,7 @@ static void _rtl92de_efuse_update_chip_version(struct ieee80211_hw *hw)
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rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "D-CUT!!!\n");
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break;
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case 0xCC33:
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case 0x33CC:
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chipver |= CHIP_92D_E_CUT;
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rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "E-CUT!!!\n");
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break;
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@ -672,15 +678,27 @@ static void _rtl92de_efuse_update_chip_version(struct ieee80211_hw *hw)
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static void _rtl92de_read_adapter_info(struct ieee80211_hw *hw)
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{
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static const int params_pci[] = {
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RTL8190_EEPROM_ID, EEPROM_VID, EEPROM_DID,
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EEPROM_SVID, EEPROM_SMID, EEPROM_MAC_ADDR_MAC0_92D,
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EEPROM_CHANNEL_PLAN, EEPROM_VERSION, EEPROM_CUSTOMER_ID,
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COUNTRY_CODE_WORLD_WIDE_13
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};
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static const int params_usb[] = {
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RTL8190_EEPROM_ID, EEPROM_VID_USB, EEPROM_PID_USB,
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EEPROM_VID_USB, EEPROM_PID_USB, EEPROM_MAC_ADDR_MAC0_92DU,
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EEPROM_CHANNEL_PLAN, EEPROM_VERSION, EEPROM_CUSTOMER_ID,
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COUNTRY_CODE_WORLD_WIDE_13
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};
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struct rtl_priv *rtlpriv = rtl_priv(hw);
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struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
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struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
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int params[] = {RTL8190_EEPROM_ID, EEPROM_VID, EEPROM_DID,
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EEPROM_SVID, EEPROM_SMID, EEPROM_MAC_ADDR_MAC0_92D,
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EEPROM_CHANNEL_PLAN, EEPROM_VERSION, EEPROM_CUSTOMER_ID,
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COUNTRY_CODE_WORLD_WIDE_13};
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const int *params = params_pci;
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u8 *hwinfo;
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if (rtlhal->interface == INTF_USB)
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params = params_usb;
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hwinfo = kzalloc(HWSET_MAX_SIZE, GFP_KERNEL);
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if (!hwinfo)
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return;
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@ -842,6 +860,7 @@ static void rtl92de_update_hal_rate_mask(struct ieee80211_hw *hw,
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struct rtl_priv *rtlpriv = rtl_priv(hw);
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struct rtl_phy *rtlphy = &rtlpriv->phy;
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struct rtl_sta_info *sta_entry = NULL;
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struct rtl92d_rate_mask_h2c rate_mask;
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enum wireless_mode wirelessmode;
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bool shortgi = false;
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u8 curshortgi_40mhz;
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@ -849,7 +868,6 @@ static void rtl92de_update_hal_rate_mask(struct ieee80211_hw *hw,
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u8 curtxbw_40mhz;
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u32 ratr_bitmap;
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u8 ratr_index;
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u32 value[2];
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u8 macid = 0;
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u8 mimo_ps;
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@ -965,12 +983,28 @@ static void rtl92de_update_hal_rate_mask(struct ieee80211_hw *hw,
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break;
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}
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value[0] = (ratr_bitmap & 0x0fffffff) | (ratr_index << 28);
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value[1] = macid | (shortgi ? 0x20 : 0x00) | 0x80;
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le32p_replace_bits(&rate_mask.rate_mask_and_raid, ratr_bitmap, RATE_MASK_MASK);
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le32p_replace_bits(&rate_mask.rate_mask_and_raid, ratr_index, RAID_MASK);
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u8p_replace_bits(&rate_mask.macid_and_short_gi, macid, MACID_MASK);
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u8p_replace_bits(&rate_mask.macid_and_short_gi, shortgi, SHORT_GI_MASK);
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u8p_replace_bits(&rate_mask.macid_and_short_gi, 1, BIT(7));
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rtl_dbg(rtlpriv, COMP_RATR, DBG_DMESG,
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"ratr_bitmap :%x value0:%x value1:%x\n",
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ratr_bitmap, value[0], value[1]);
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rtl92d_fill_h2c_cmd(hw, H2C_RA_MASK, 5, (u8 *)value);
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"Rate_index:%x, ratr_val:%x, %5phC\n",
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ratr_index, ratr_bitmap, &rate_mask);
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if (rtlhal->interface == INTF_PCI) {
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rtl92d_fill_h2c_cmd(hw, H2C_RA_MASK, sizeof(rate_mask),
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(u8 *)&rate_mask);
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} else {
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/* rtl92d_fill_h2c_cmd() does USB I/O and will result in a
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* "scheduled while atomic" if called directly
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*/
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memcpy(rtlpriv->rate_mask, &rate_mask,
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sizeof(rtlpriv->rate_mask));
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schedule_work(&rtlpriv->works.fill_h2c_cmd);
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}
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if (macid != 0)
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sta_entry->ratr_index = ratr_index;
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}
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@ -1014,7 +1048,8 @@ bool rtl92de_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid)
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bool actuallyset = false;
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unsigned long flag;
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if (rtlpci->being_init_adapter)
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if (rtlpriv->rtlhal.interface == INTF_PCI &&
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rtlpci->being_init_adapter)
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return false;
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if (ppsc->swrf_processing)
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return false;
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@ -89,11 +89,11 @@ u32 rtl92d_phy_query_rf_reg(struct ieee80211_hw *hw, enum radio_path rfpath,
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rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
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"regaddr(%#x), rfpath(%#x), bitmask(%#x)\n",
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regaddr, rfpath, bitmask);
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spin_lock(&rtlpriv->locks.rf_lock);
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rtl92d_pci_lock(rtlpriv);
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original_value = _rtl92d_phy_rf_serial_read(hw, rfpath, regaddr);
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bitshift = calculate_bit_shift(bitmask);
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readback_value = (original_value & bitmask) >> bitshift;
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spin_unlock(&rtlpriv->locks.rf_lock);
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rtl92d_pci_unlock(rtlpriv);
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rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
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"regaddr(%#x), rfpath(%#x), bitmask(%#x), original_value(%#x)\n",
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regaddr, rfpath, bitmask, original_value);
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@ -113,7 +113,7 @@ void rtl92d_phy_set_rf_reg(struct ieee80211_hw *hw, enum radio_path rfpath,
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regaddr, bitmask, data, rfpath);
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if (bitmask == 0)
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return;
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spin_lock(&rtlpriv->locks.rf_lock);
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rtl92d_pci_lock(rtlpriv);
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if (rtlphy->rf_mode != RF_OP_BY_FW) {
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if (bitmask != RFREG_OFFSET_MASK) {
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original_value = _rtl92d_phy_rf_serial_read(hw,
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@ -125,7 +125,7 @@ void rtl92d_phy_set_rf_reg(struct ieee80211_hw *hw, enum radio_path rfpath,
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}
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_rtl92d_phy_rf_serial_write(hw, rfpath, regaddr, data);
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}
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spin_unlock(&rtlpriv->locks.rf_lock);
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rtl92d_pci_unlock(rtlpriv);
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rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
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"regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
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regaddr, bitmask, data, rfpath);
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@ -650,6 +650,8 @@ static void rtl92d_phy_set_io(struct ieee80211_hw *hw)
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case IO_CMD_PAUSE_DM_BY_SCAN:
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rtlphy->initgain_backup.xaagccore1 = de_digtable->cur_igvalue;
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de_digtable->cur_igvalue = 0x37;
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if (rtlpriv->rtlhal.interface == INTF_USB)
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de_digtable->cur_igvalue = 0x17;
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rtl92d_dm_write_dig(hw);
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break;
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default:
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@ -710,22 +712,28 @@ void rtl92d_phy_config_macphymode(struct ieee80211_hw *hw)
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struct rtl_priv *rtlpriv = rtl_priv(hw);
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struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
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u8 offset = REG_MAC_PHY_CTRL_NORMAL;
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u8 phy_ctrl = 0xf0;
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if (rtlhal->interface == INTF_USB) {
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phy_ctrl = rtl_read_byte(rtlpriv, offset);
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phy_ctrl &= ~(BIT(0) | BIT(1) | BIT(2));
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}
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switch (rtlhal->macphymode) {
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case DUALMAC_DUALPHY:
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rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
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"MacPhyMode: DUALMAC_DUALPHY\n");
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rtl_write_byte(rtlpriv, offset, 0xF3);
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rtl_write_byte(rtlpriv, offset, phy_ctrl | BIT(0) | BIT(1));
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break;
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case SINGLEMAC_SINGLEPHY:
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rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
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"MacPhyMode: SINGLEMAC_SINGLEPHY\n");
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rtl_write_byte(rtlpriv, offset, 0xF4);
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rtl_write_byte(rtlpriv, offset, phy_ctrl | BIT(2));
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break;
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case DUALMAC_SINGLEPHY:
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rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
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"MacPhyMode: DUALMAC_SINGLEPHY\n");
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rtl_write_byte(rtlpriv, offset, 0xF1);
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rtl_write_byte(rtlpriv, offset, phy_ctrl | BIT(0));
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break;
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}
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}
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@ -32,6 +32,9 @@ static inline void rtl92d_acquire_cckandrw_pagea_ctl(struct ieee80211_hw *hw,
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{
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struct rtl_priv *rtlpriv = rtl_priv(hw);
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if (rtlpriv->rtlhal.interface == INTF_USB)
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return;
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if (rtlpriv->rtlhal.interfaceindex == 1)
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spin_lock_irqsave(&rtlpriv->locks.cck_and_rw_pagea_lock, *flag);
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}
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@ -41,6 +44,9 @@ static inline void rtl92d_release_cckandrw_pagea_ctl(struct ieee80211_hw *hw,
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{
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struct rtl_priv *rtlpriv = rtl_priv(hw);
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if (rtlpriv->rtlhal.interface == INTF_USB)
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return;
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if (rtlpriv->rtlhal.interfaceindex == 1)
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spin_unlock_irqrestore(&rtlpriv->locks.cck_and_rw_pagea_lock,
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*flag);
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@ -84,4 +90,22 @@ void rtl92d_acquire_cckandrw_pagea_ctl(struct ieee80211_hw *hw,
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void rtl92d_release_cckandrw_pagea_ctl(struct ieee80211_hw *hw,
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unsigned long *flag);
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/* Without these helpers and the declarations sparse warns about
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* context imbalance.
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*/
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static inline void rtl92d_pci_lock(struct rtl_priv *rtlpriv)
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{
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if (rtlpriv->rtlhal.interface == INTF_PCI)
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spin_lock(&rtlpriv->locks.rf_lock);
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}
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static inline void rtl92d_pci_unlock(struct rtl_priv *rtlpriv)
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{
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if (rtlpriv->rtlhal.interface == INTF_PCI)
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spin_unlock(&rtlpriv->locks.rf_lock);
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}
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void rtl92d_pci_lock(struct rtl_priv *rtlpriv);
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void rtl92d_pci_unlock(struct rtl_priv *rtlpriv);
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#endif
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@ -52,6 +52,8 @@
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#define REG_HMEBOX_EXT_3 0x008E
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#define SIZE_OF_REG_HMEBOX_EXT 2
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#define REG_EFUSE_ACCESS 0x00CF
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#define REG_BIST_SCAN 0x00D0
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#define REG_BIST_RPT 0x00D4
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#define REG_BIST_ROM_RPT 0x00D8
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@ -87,6 +89,7 @@
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#define REG_CPWM 0x012F
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#define REG_FWIMR 0x0130
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#define REG_FWISR 0x0134
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#define REG_FTIMR 0x0138
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#define REG_PKTBUF_DBG_CTRL 0x0140
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#define REG_PKTBUF_DBG_DATA_L 0x0144
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#define REG_PKTBUF_DBG_DATA_H 0x0148
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@ -199,6 +202,8 @@
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#define REG_POWER_STAGE1 0x04B4
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#define REG_POWER_STAGE2 0x04B8
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#define REG_PKT_LIFE_TIME 0x04C0
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#define REG_PKT_VO_VI_LIFE_TIME 0x04C0
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#define REG_PKT_BE_BK_LIFE_TIME 0x04C2
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#define REG_STBC_SETTING 0x04C4
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#define REG_PROT_MODE_CTRL 0x04C8
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#define REG_MAX_AGGR_NUM 0x04CA
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@ -235,6 +240,7 @@
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#define REG_RD_NAV_NXT 0x0544
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#define REG_NAV_PROT_LEN 0x0546
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#define REG_BCN_CTRL 0x0550
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#define REG_BCN_CTRL_1 0x0551
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#define REG_MBID_NUM 0x0552
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#define REG_DUAL_TSF_RST 0x0553
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#define REG_BCN_INTERVAL 0x0554
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@ -321,6 +327,8 @@
|
|||
#define REG_BT_COEX_TABLE 0x06C0
|
||||
#define REG_WMAC_RESP_TXINFO 0x06D8
|
||||
|
||||
#define REG_USB_Queue_Select_MAC0 0xFE44
|
||||
#define REG_USB_Queue_Select_MAC1 0xFE47
|
||||
|
||||
/* ----------------------------------------------------- */
|
||||
/* Redifine 8192C register definition for compatibility */
|
||||
|
|
@ -357,27 +365,27 @@
|
|||
#define RRSR_RSC_UPSUBCHNL 0x400000
|
||||
#define RRSR_RSC_LOWSUBCHNL 0x200000
|
||||
#define RRSR_SHORT 0x800000
|
||||
#define RRSR_1M BIT0
|
||||
#define RRSR_2M BIT1
|
||||
#define RRSR_5_5M BIT2
|
||||
#define RRSR_11M BIT3
|
||||
#define RRSR_6M BIT4
|
||||
#define RRSR_9M BIT5
|
||||
#define RRSR_12M BIT6
|
||||
#define RRSR_18M BIT7
|
||||
#define RRSR_24M BIT8
|
||||
#define RRSR_36M BIT9
|
||||
#define RRSR_48M BIT10
|
||||
#define RRSR_54M BIT11
|
||||
#define RRSR_MCS0 BIT12
|
||||
#define RRSR_MCS1 BIT13
|
||||
#define RRSR_MCS2 BIT14
|
||||
#define RRSR_MCS3 BIT15
|
||||
#define RRSR_MCS4 BIT16
|
||||
#define RRSR_MCS5 BIT17
|
||||
#define RRSR_MCS6 BIT18
|
||||
#define RRSR_MCS7 BIT19
|
||||
#define BRSR_ACKSHORTPMB BIT23
|
||||
#define RRSR_1M BIT(0)
|
||||
#define RRSR_2M BIT(1)
|
||||
#define RRSR_5_5M BIT(2)
|
||||
#define RRSR_11M BIT(3)
|
||||
#define RRSR_6M BIT(4)
|
||||
#define RRSR_9M BIT(5)
|
||||
#define RRSR_12M BIT(6)
|
||||
#define RRSR_18M BIT(7)
|
||||
#define RRSR_24M BIT(8)
|
||||
#define RRSR_36M BIT(9)
|
||||
#define RRSR_48M BIT(10)
|
||||
#define RRSR_54M BIT(11)
|
||||
#define RRSR_MCS0 BIT(12)
|
||||
#define RRSR_MCS1 BIT(13)
|
||||
#define RRSR_MCS2 BIT(14)
|
||||
#define RRSR_MCS3 BIT(15)
|
||||
#define RRSR_MCS4 BIT(16)
|
||||
#define RRSR_MCS5 BIT(17)
|
||||
#define RRSR_MCS6 BIT(18)
|
||||
#define RRSR_MCS7 BIT(19)
|
||||
#define BRSR_ACKSHORTPMB BIT(23)
|
||||
|
||||
/* ----------------------------------------------------- */
|
||||
/* 8192C Rate Definition */
|
||||
|
|
@ -602,7 +610,11 @@
|
|||
#define EEPROM_SVID 0x2C /* SE Vendor ID.E-F */
|
||||
#define EEPROM_SMID 0x2E /* SE PCI Subsystem ID. 10-11 */
|
||||
|
||||
#define EEPROM_VID_USB 0xC
|
||||
#define EEPROM_PID_USB 0xE
|
||||
#define EEPROM_ENDPOINT_SETTING 0x10
|
||||
#define EEPROM_MAC_ADDR 0x16 /* SEMAC Address. 12-17 */
|
||||
#define EEPROM_MAC_ADDR_MAC0_92DU 0x19
|
||||
#define EEPROM_MAC_ADDR_MAC0_92D 0x55
|
||||
#define EEPROM_MAC_ADDR_MAC1_92D 0x5B
|
||||
|
||||
|
|
@ -917,6 +929,42 @@
|
|||
#define BD_HCI_SEL BIT(26)
|
||||
#define TYPE_ID BIT(27)
|
||||
|
||||
#define HCI_TXDMA_EN BIT(0)
|
||||
#define HCI_RXDMA_EN BIT(1)
|
||||
#define TXDMA_EN BIT(2)
|
||||
#define RXDMA_EN BIT(3)
|
||||
#define PROTOCOL_EN BIT(4)
|
||||
#define SCHEDULE_EN BIT(5)
|
||||
#define MACTXEN BIT(6)
|
||||
#define MACRXEN BIT(7)
|
||||
#define ENSWBCN BIT(8)
|
||||
#define ENSEC BIT(9)
|
||||
|
||||
#define HQSEL_VOQ BIT(0)
|
||||
#define HQSEL_VIQ BIT(1)
|
||||
#define HQSEL_BEQ BIT(2)
|
||||
#define HQSEL_BKQ BIT(3)
|
||||
#define HQSEL_MGTQ BIT(4)
|
||||
#define HQSEL_HIQ BIT(5)
|
||||
|
||||
#define TXDMA_HIQ_MAP GENMASK(15, 14)
|
||||
#define TXDMA_MGQ_MAP GENMASK(13, 12)
|
||||
#define TXDMA_BKQ_MAP GENMASK(11, 10)
|
||||
#define TXDMA_BEQ_MAP GENMASK(9, 8)
|
||||
#define TXDMA_VIQ_MAP GENMASK(7, 6)
|
||||
#define TXDMA_VOQ_MAP GENMASK(5, 4)
|
||||
|
||||
#define QUEUE_LOW 1
|
||||
#define QUEUE_NORMAL 2
|
||||
#define QUEUE_HIGH 3
|
||||
|
||||
#define HPQ_MASK GENMASK(7, 0)
|
||||
#define LPQ_MASK GENMASK(15, 8)
|
||||
#define PUBQ_MASK GENMASK(23, 16)
|
||||
#define LD_RQPN BIT(31)
|
||||
|
||||
#define DROP_DATA_EN BIT(9)
|
||||
|
||||
/* LLT_INIT */
|
||||
#define _LLT_NO_ACTIVE 0x0
|
||||
#define _LLT_WRITE_ACCESS 0x1
|
||||
|
|
@ -931,6 +979,10 @@
|
|||
/* ----------------------------------------------------- */
|
||||
/* 0x0400h ~ 0x047Fh Protocol Configuration */
|
||||
/* ----------------------------------------------------- */
|
||||
/* FWHW_TXQ_CTRL */
|
||||
#define EN_AMPDU_RTY_NEW BIT(7)
|
||||
#define EN_BCNQ_DL BIT(22)
|
||||
|
||||
#define RETRY_LIMIT_SHORT_SHIFT 8
|
||||
#define RETRY_LIMIT_LONG_SHIFT 0
|
||||
|
||||
|
|
@ -944,6 +996,13 @@
|
|||
#define AC_PARAM_ECW_MIN_OFFSET 8
|
||||
#define AC_PARAM_AIFS_OFFSET 0
|
||||
|
||||
/* REG_RD_CTRL */
|
||||
#define DIS_EDCA_CNT_DWN BIT(11)
|
||||
|
||||
/* REG_BCN_CTRL */
|
||||
#define EN_BCN_FUNCTION BIT(3)
|
||||
#define DIS_TSF_UDT BIT(4)
|
||||
|
||||
/* ACMHWCTRL */
|
||||
#define ACMHW_HWEN BIT(0)
|
||||
#define ACMHW_BEQEN BIT(1)
|
||||
|
|
@ -1075,6 +1134,11 @@
|
|||
#define RCCK0_FACOUNTERLOWER 0xa5c
|
||||
#define RCCK0_FACOUNTERUPPER 0xa58
|
||||
|
||||
#define RPDP_ANTA 0xb00
|
||||
#define RCONFIG_ANTA 0xb68
|
||||
#define RCONFIG_ANTB 0xb6c
|
||||
#define RPDP_ANTB 0xb70
|
||||
|
||||
/* 6. PageC(0xC00) */
|
||||
#define ROFDM0_LSTF 0xc00
|
||||
|
||||
|
|
@ -1128,6 +1192,7 @@
|
|||
#define ROFDM0_TXPSEUDONOISEWGT 0xce4
|
||||
#define ROFDM0_FRAMESYNC 0xcf0
|
||||
#define ROFDM0_DFSREPORT 0xcf4
|
||||
#define ROFDM0_RXIQEXTANTA 0xca0
|
||||
#define ROFDM0_TXCOEFF1 0xca4
|
||||
#define ROFDM0_TXCOEFF2 0xca8
|
||||
#define ROFDM0_TXCOEFF3 0xcac
|
||||
|
|
@ -1186,17 +1251,70 @@
|
|||
#define RTXAGC_B_MCS15_MCS12 0x868
|
||||
#define RTXAGC_B_CCK11_A_CCK2_11 0x86c
|
||||
|
||||
#define RFPGA0_IQK 0xe28
|
||||
#define RTX_IQK_TONE_A 0xe30
|
||||
#define RRX_IQK_TONE_A 0xe34
|
||||
#define RTX_IQK_PI_A 0xe38
|
||||
#define RRX_IQK_PI_A 0xe3c
|
||||
|
||||
#define RTX_IQK 0xe40
|
||||
#define RRX_IQK 0xe44
|
||||
#define RIQK_AGC_PTS 0xe48
|
||||
#define RIQK_AGC_RSP 0xe4c
|
||||
#define RTX_IQK_TONE_B 0xe50
|
||||
#define RRX_IQK_TONE_B 0xe54
|
||||
#define RTX_IQK_PI_B 0xe58
|
||||
#define RRX_IQK_PI_B 0xe5c
|
||||
#define RIQK_AGC_CONT 0xe60
|
||||
|
||||
#define RBLUE_TOOTH 0xe6c
|
||||
#define RRX_WAIT_CCA 0xe70
|
||||
#define RTX_CCK_RFON 0xe74
|
||||
#define RTX_CCK_BBON 0xe78
|
||||
#define RTX_OFDM_RFON 0xe7c
|
||||
#define RTX_OFDM_BBON 0xe80
|
||||
#define RTX_TO_RX 0xe84
|
||||
#define RTX_TO_TX 0xe88
|
||||
#define RRX_CCK 0xe8c
|
||||
|
||||
#define RTX_POWER_BEFORE_IQK_A 0xe94
|
||||
#define RTX_POWER_AFTER_IQK_A 0xe9c
|
||||
|
||||
#define RRX_POWER_BEFORE_IQK_A 0xea0
|
||||
#define RRX_POWER_BEFORE_IQK_A_2 0xea4
|
||||
#define RRX_POWER_AFTER_IQK_A 0xea8
|
||||
#define RRX_POWER_AFTER_IQK_A_2 0xeac
|
||||
|
||||
#define RTX_POWER_BEFORE_IQK_B 0xeb4
|
||||
#define RTX_POWER_AFTER_IQK_B 0xebc
|
||||
|
||||
#define RRX_POWER_BEFORE_IQK_B 0xec0
|
||||
#define RRX_POWER_BEFORE_IQK_B_2 0xec4
|
||||
#define RRX_POWER_AFTER_IQK_B 0xec8
|
||||
#define RRX_POWER_AFTER_IQK_B_2 0xecc
|
||||
|
||||
#define MASK_IQK_RESULT 0x03ff0000
|
||||
|
||||
#define RRX_OFDM 0xed0
|
||||
#define RRX_WAIT_RIFS 0xed4
|
||||
#define RRX_TO_RX 0xed8
|
||||
#define RSTANDBY 0xedc
|
||||
#define RSLEEP 0xee0
|
||||
#define RPMPD_ANAEN 0xeec
|
||||
|
||||
/* RL6052 Register definition */
|
||||
#define RF_AC 0x00
|
||||
|
||||
#define RF_IQADJ_G1 0x01
|
||||
#define RF_IQADJ_G2 0x02
|
||||
#define RF_BS_PA_APSET_G1_G4 0x03
|
||||
#define RF_POW_TRSW 0x05
|
||||
|
||||
#define RF_GAIN_RX 0x06
|
||||
#define RF_GAIN_TX 0x07
|
||||
|
||||
#define RF_TXM_IDAC 0x08
|
||||
#define RF_TXPA_AG 0x0B
|
||||
#define RF_BS_IQGEN 0x0F
|
||||
|
||||
#define RF_MODE1 0x10
|
||||
|
|
|
|||
|
|
@ -979,6 +979,9 @@ int rtl_usb_probe(struct usb_interface *intf,
|
|||
usb_priv->dev.intf = intf;
|
||||
usb_priv->dev.udev = udev;
|
||||
usb_set_intfdata(intf, hw);
|
||||
/* For dual MAC RTL8192DU, which has two interfaces. */
|
||||
rtlpriv->rtlhal.interfaceindex =
|
||||
intf->altsetting[0].desc.bInterfaceNumber;
|
||||
/* init cfg & intf_ops */
|
||||
rtlpriv->rtlhal.interface = INTF_USB;
|
||||
rtlpriv->cfg = rtl_hal_cfg;
|
||||
|
|
|
|||
|
|
@ -20,6 +20,7 @@
|
|||
#define MASKBYTE1 0xff00
|
||||
#define MASKBYTE2 0xff0000
|
||||
#define MASKBYTE3 0xff000000
|
||||
#define MASKH3BYTES 0xffffff00
|
||||
#define MASKHWORD 0xffff0000
|
||||
#define MASKLWORD 0x0000ffff
|
||||
#define MASKDWORD 0xffffffff
|
||||
|
|
@ -48,6 +49,10 @@
|
|||
#define MASK20BITS 0xfffff
|
||||
#define RFREG_OFFSET_MASK 0xfffff
|
||||
|
||||
/* For dual MAC RTL8192DU */
|
||||
#define MAC0_ACCESS_PHY1 0x4000
|
||||
#define MAC1_ACCESS_PHY0 0x2000
|
||||
|
||||
#define RF_CHANGE_BY_INIT 0
|
||||
#define RF_CHANGE_BY_IPS BIT(28)
|
||||
#define RF_CHANGE_BY_PS BIT(29)
|
||||
|
|
|
|||
Loading…
Reference in New Issue