EDAC/amd64: Limit error injection functionality to supported hw
Families up to and including 0x16 allow access to the injection hardware. Starting with family 0x17, access to those registers is blocked by security policy. Limit that only on the families which support it. Suggested-by: Yazen Ghannam <yazen.ghannam@amd.com> Signed-off-by: Borislav Petkov <bp@suse.de> Link: https://lkml.kernel.org/r/20201222180013.GD13463@zn.tnic
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@ -84,10 +84,10 @@ config EDAC_AMD64
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When EDAC_DEBUG is enabled, hardware error injection facilities
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through sysfs are available:
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Recent Opterons (Family 10h and later) provide for Memory Error
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Injection into the ECC detection circuits. The amd64_edac module
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allows the operator/user to inject Uncorrectable and Correctable
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errors into DRAM.
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AMD CPUs up to and excluding family 0x17 provide for Memory
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Error Injection into the ECC detection circuits. The amd64_edac
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module allows the operator/user to inject Uncorrectable and
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Correctable errors into DRAM.
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When enabled, in each of the respective memory controller directories
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(/sys/devices/system/edac/mc/mcX), there are 3 input files:
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@ -828,9 +828,11 @@ static umode_t inj_is_visible(struct kobject *kobj, struct attribute *attr, int
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struct mem_ctl_info *mci = container_of(dev, struct mem_ctl_info, dev);
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struct amd64_pvt *pvt = mci->pvt_info;
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if (pvt->fam < 0x10)
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return 0;
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return attr->mode;
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/* Families which have that injection hw */
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if (pvt->fam >= 0x10 && pvt->fam <= 0x16)
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return attr->mode;
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return 0;
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}
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static const struct attribute_group inj_group = {
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