Miscellaneous fixes:
- Fix possible memory leak the riscv-intc irqchip driver load failures - Fix boot crash in the sifive-plic irqchip driver caused by recently changed boot initialization order - Fix race condition in the gic-v3-its irqchip driver Signed-off-by: Ingo Molnar <mingo@kernel.org> -----BEGIN PGP SIGNATURE----- iQJFBAABCgAvFiEEBpT5eoXrXCwVQwEKEnMQ0APhK1gFAmZkDTMRHG1pbmdvQGtl cm5lbC5vcmcACgkQEnMQ0APhK1hPsRAAoHgcHw9KGhI9+y7Xnnjt4W9Ud6S3W8cs AcmP9x83+iilnPQrrWlB/v5p02qBPPdpqnDvOnB/7bITxJGxnSBXj1awUuV45qX2 QRS4sIDq6zkDH6pX0diiwqLbfWZwpcbvtnR3nXSGImOK0jI3yQiSLEc8vswt88Jr HnYg9UdvKCt7j+jbqf9PzPHJP8z/U+Kx6eMPF4H/6R+nccedtQ0D2BdR5RSKFVZM aQwpZp6LTTapp3B1lXOx6IJaVTkRMeEm9J2Zc4R/pD3dvKof0xpEwJ+dqBrPAjb0 +ospUJcPz4Sw9XhBIrqq4A+LUewiVa9grI3t1qit+VtbXkVHfLK9mUlyXfQzgMFz JTlUgt3V4vpbceUbFZsefXeB2TDGAPpFQvwgNozvEx+IgEZjryrSa2SgAuhl4Y6b nIxwBYFMlG6GI8CIDVGyl3XK/DcKUXM1XloJwTRDWjN/cZloxaZjRIpIiACr+SYW S1axryYDqDG4VU3vfTEqb75VGm4rPtHLXqRDmu/ZL8/BIQ7CQqnD0eMGIQ79aEXj Ia5CccTWqu0dufA5rxl47lcacPEKYlVFTkTul1ujzM2ymllmwjTpPKvSEhcwUC6J XRR7iv372AUo1xnk1G34Wl6Mp9nbxW2DXNinX/eDuV0AqV/1EKxs6vqgddGKhOuX K+ER8F+is64= =98O/ -----END PGP SIGNATURE----- Merge tag 'irq-urgent-2024-06-08' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull irq fixes from Ingo Molnar: - Fix possible memory leak the riscv-intc irqchip driver load failures - Fix boot crash in the sifive-plic irqchip driver caused by recently changed boot initialization order - Fix race condition in the gic-v3-its irqchip driver * tag 'irq-urgent-2024-06-08' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: irqchip/gic-v3-its: Fix potential race condition in its_vlpi_prop_update() irqchip/sifive-plic: Chain to parent IRQ after handlers are ready irqchip/riscv-intc: Prevent memory leak when riscv_intc_init_common() fails
This commit is contained in:
commit
36714d69b1
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@ -1846,28 +1846,22 @@ static int its_vlpi_map(struct irq_data *d, struct its_cmd_info *info)
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{
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struct its_device *its_dev = irq_data_get_irq_chip_data(d);
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u32 event = its_get_event_id(d);
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int ret = 0;
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if (!info->map)
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return -EINVAL;
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raw_spin_lock(&its_dev->event_map.vlpi_lock);
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if (!its_dev->event_map.vm) {
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struct its_vlpi_map *maps;
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maps = kcalloc(its_dev->event_map.nr_lpis, sizeof(*maps),
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GFP_ATOMIC);
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if (!maps) {
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ret = -ENOMEM;
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goto out;
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}
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if (!maps)
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return -ENOMEM;
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its_dev->event_map.vm = info->map->vm;
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its_dev->event_map.vlpi_maps = maps;
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} else if (its_dev->event_map.vm != info->map->vm) {
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ret = -EINVAL;
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goto out;
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return -EINVAL;
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}
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/* Get our private copy of the mapping information */
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@ -1899,46 +1893,32 @@ static int its_vlpi_map(struct irq_data *d, struct its_cmd_info *info)
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its_dev->event_map.nr_vlpis++;
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}
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out:
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raw_spin_unlock(&its_dev->event_map.vlpi_lock);
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return ret;
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return 0;
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}
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static int its_vlpi_get(struct irq_data *d, struct its_cmd_info *info)
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{
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struct its_device *its_dev = irq_data_get_irq_chip_data(d);
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struct its_vlpi_map *map;
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int ret = 0;
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raw_spin_lock(&its_dev->event_map.vlpi_lock);
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map = get_vlpi_map(d);
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if (!its_dev->event_map.vm || !map) {
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ret = -EINVAL;
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goto out;
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}
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if (!its_dev->event_map.vm || !map)
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return -EINVAL;
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/* Copy our mapping information to the incoming request */
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*info->map = *map;
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out:
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raw_spin_unlock(&its_dev->event_map.vlpi_lock);
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return ret;
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return 0;
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}
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static int its_vlpi_unmap(struct irq_data *d)
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{
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struct its_device *its_dev = irq_data_get_irq_chip_data(d);
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u32 event = its_get_event_id(d);
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int ret = 0;
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raw_spin_lock(&its_dev->event_map.vlpi_lock);
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if (!its_dev->event_map.vm || !irqd_is_forwarded_to_vcpu(d)) {
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ret = -EINVAL;
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goto out;
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}
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if (!its_dev->event_map.vm || !irqd_is_forwarded_to_vcpu(d))
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return -EINVAL;
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/* Drop the virtual mapping */
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its_send_discard(its_dev, event);
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@ -1962,9 +1942,7 @@ static int its_vlpi_unmap(struct irq_data *d)
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kfree(its_dev->event_map.vlpi_maps);
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}
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out:
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raw_spin_unlock(&its_dev->event_map.vlpi_lock);
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return ret;
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return 0;
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}
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static int its_vlpi_prop_update(struct irq_data *d, struct its_cmd_info *info)
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@ -1992,6 +1970,8 @@ static int its_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu_info)
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if (!is_v4(its_dev->its))
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return -EINVAL;
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guard(raw_spinlock_irq)(&its_dev->event_map.vlpi_lock);
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/* Unmap request? */
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if (!info)
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return its_vlpi_unmap(d);
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@ -253,8 +253,9 @@ IRQCHIP_DECLARE(andes, "andestech,cpu-intc", riscv_intc_init);
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static int __init riscv_intc_acpi_init(union acpi_subtable_headers *header,
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const unsigned long end)
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{
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struct fwnode_handle *fn;
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struct acpi_madt_rintc *rintc;
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struct fwnode_handle *fn;
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int rc;
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rintc = (struct acpi_madt_rintc *)header;
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@ -273,7 +274,11 @@ static int __init riscv_intc_acpi_init(union acpi_subtable_headers *header,
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return -ENOMEM;
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}
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return riscv_intc_init_common(fn, &riscv_intc_chip);
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rc = riscv_intc_init_common(fn, &riscv_intc_chip);
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if (rc)
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irq_domain_free_fwnode(fn);
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return rc;
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}
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IRQCHIP_ACPI_DECLARE(riscv_intc, ACPI_MADT_TYPE_RINTC, NULL,
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@ -85,7 +85,7 @@ struct plic_handler {
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struct plic_priv *priv;
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};
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static int plic_parent_irq __ro_after_init;
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static bool plic_cpuhp_setup_done __ro_after_init;
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static bool plic_global_setup_done __ro_after_init;
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static DEFINE_PER_CPU(struct plic_handler, plic_handlers);
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static int plic_irq_set_type(struct irq_data *d, unsigned int type);
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@ -487,10 +487,8 @@ static int plic_probe(struct platform_device *pdev)
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unsigned long plic_quirks = 0;
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struct plic_handler *handler;
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u32 nr_irqs, parent_hwirq;
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struct irq_domain *domain;
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struct plic_priv *priv;
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irq_hw_number_t hwirq;
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bool cpuhp_setup;
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if (is_of_node(dev->fwnode)) {
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const struct of_device_id *id;
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@ -549,14 +547,6 @@ static int plic_probe(struct platform_device *pdev)
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continue;
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}
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/* Find parent domain and register chained handler */
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domain = irq_find_matching_fwnode(riscv_get_intc_hwnode(), DOMAIN_BUS_ANY);
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if (!plic_parent_irq && domain) {
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plic_parent_irq = irq_create_mapping(domain, RV_IRQ_EXT);
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if (plic_parent_irq)
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irq_set_chained_handler(plic_parent_irq, plic_handle_irq);
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}
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/*
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* When running in M-mode we need to ignore the S-mode handler.
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* Here we assume it always comes later, but that might be a
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goto fail_cleanup_contexts;
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/*
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* We can have multiple PLIC instances so setup cpuhp state
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* We can have multiple PLIC instances so setup global state
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* and register syscore operations only once after context
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* handlers of all online CPUs are initialized.
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*/
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if (!plic_cpuhp_setup_done) {
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cpuhp_setup = true;
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if (!plic_global_setup_done) {
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struct irq_domain *domain;
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bool global_setup = true;
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for_each_online_cpu(cpu) {
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handler = per_cpu_ptr(&plic_handlers, cpu);
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if (!handler->present) {
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cpuhp_setup = false;
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global_setup = false;
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break;
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}
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}
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if (cpuhp_setup) {
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if (global_setup) {
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/* Find parent domain and register chained handler */
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domain = irq_find_matching_fwnode(riscv_get_intc_hwnode(), DOMAIN_BUS_ANY);
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if (domain)
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plic_parent_irq = irq_create_mapping(domain, RV_IRQ_EXT);
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if (plic_parent_irq)
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irq_set_chained_handler(plic_parent_irq, plic_handle_irq);
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cpuhp_setup_state(CPUHP_AP_IRQ_SIFIVE_PLIC_STARTING,
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"irqchip/sifive/plic:starting",
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plic_starting_cpu, plic_dying_cpu);
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register_syscore_ops(&plic_irq_syscore_ops);
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plic_cpuhp_setup_done = true;
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plic_global_setup_done = true;
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}
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}
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