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[ARM] 5293/1: ep93xx: add defines for external chipselects 

This patch adds defines for the external chipselect physical base
addresses available with the EP93xx. These are meant to be used
in the platform init code.

In addition, documentation about the synchronous/asynchronous boot
modes for the EP93xx and a reference to errata about issues with
synchronous booting has been added.

Signed-off-by: <H Hartley Sweeten <hsweeten@visionengravers.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Hartley Sweeten 2008-10-06 22:43:02 +01:00 committed by Russell King
parent a0a08fdca5
commit 446b097a42
1 changed files with 34 additions and 0 deletions
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34
arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h
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@ -5,6 +5,40 @@
#ifndef __ASM_ARCH_EP93XX_REGS_H
#define __ASM_ARCH_EP93XX_REGS_H
/*
* EP93xx Physical Memory Map:
*
* The ASDO pin is sampled at system reset to select a synchronous or
* asynchronous boot configuration. When ASDO is "1" (i.e. pulled-up)
* the synchronous boot mode is selected. When ASDO is "0" (i.e
* pulled-down) the asynchronous boot mode is selected.
*
* In synchronous boot mode nSDCE3 is decoded starting at physical address
* 0x00000000 and nCS0 is decoded starting at 0xf0000000. For asynchronous
* boot mode they are swapped with nCS0 decoded at 0x00000000 ann nSDCE3
* decoded at 0xf0000000.
*
* There is known errata for the EP93xx dealing with External Memory
* Configurations. Please refer to "AN273: EP93xx Silicon Rev E Design
* Guidelines" for more information. This document can be found at:
*
* http://www.cirrus.com/en/pubs/appNote/AN273REV4.pdf
*/
#define EP93XX_CS0_PHYS_BASE_ASYNC 0x00000000 /* ASDO Pin = 0 */
#define EP93XX_SDCE3_PHYS_BASE_SYNC 0x00000000 /* ASDO Pin = 1 */
#define EP93XX_CS1_PHYS_BASE 0x10000000
#define EP93XX_CS2_PHYS_BASE 0x20000000
#define EP93XX_CS3_PHYS_BASE 0x30000000
#define EP93XX_PCMCIA_PHYS_BASE 0x40000000
#define EP93XX_CS6_PHYS_BASE 0x60000000
#define EP93XX_CS7_PHYS_BASE 0x70000000
#define EP93XX_SDCE0_PHYS_BASE 0xc0000000
#define EP93XX_SDCE1_PHYS_BASE 0xd0000000
#define EP93XX_SDCE2_PHYS_BASE 0xe0000000
#define EP93XX_SDCE3_PHYS_BASE_ASYNC 0xf0000000 /* ASDO Pin = 0 */
#define EP93XX_CS0_PHYS_BASE_SYNC 0xf0000000 /* ASDO Pin = 1 */
/*
* EP93xx linux memory map:
*