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[ARM] 3309/1: disable the pre-ARMv5 NPTL kernel helper in the non MMU case 

Patch from Nicolas Pitre

The cmpxchg emulation on pre-ARMv5 relies on user code executed from a
kernel address.  If the operation cannot complete atomically, it is
aborted from the usr_entry macro by clearing the Z flag.  This clearing
of the Z flag is done whenever the user pc is above TASK_SIZE.

However this "pc >= TASK_SIZE" test cannot work in the non MMU case.
Worse: the current code will corrupt the Z flag on every entry to the
kernel.

Let's disable it in the non MMU case for now.  Using NPTL on non MMU
targets needs to be worked out anyway.

Signed-off-by: Nicolas Pitre <nico@cam.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Nicolas Pitre 2006-02-08 21:19:37 +00:00 committed by Russell King
parent 99595d0237
commit 49bca4c281
1 changed files with 10 additions and 0 deletions
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10
arch/arm/kernel/entry-armv.S
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@ -333,9 +333,13 @@ __pabt_svc:
@ from the exception stack
#if __LINUX_ARM_ARCH__ < 6 && !defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG)
#ifndef CONFIG_MMU
#warning "NPTL on non MMU needs fixing"
#else
@ make sure our user space atomic helper is aborted
cmp r2, #TASK_SIZE
bichs r3, r3, #PSR_Z_BIT
#endif
#endif
@
@ -756,12 +760,18 @@ __kuser_cmpxchg: @ 0xffff0fc0
* exception happening just after the str instruction which would
* clear the Z flag although the exchange was done.
*/
#ifdef CONFIG_MMU
teq ip, ip @ set Z flag
ldr ip, [r2] @ load current val
add r3, r2, #1 @ prepare store ptr
teqeq ip, r0 @ compare with oldval if still allowed
streq r1, [r3, #-1]! @ store newval if still allowed
subs r0, r2, r3 @ if r2 == r3 the str occured
#else
#warning "NPTL on non MMU needs fixing"
mov r0, #-1
adds r0, r0, #0
#endif
mov pc, lr
#else