- Improve the check whether the kernel supports WP mappings so that it
can accomodate a XenPV guest due to how the latter is setting up the PAT machinery Now that the retbleed nightmare is public, here's the first round of fallout fixes: - Fix a build failure on 32-bit due to missing include - Remove an untraining point in espfix64 return path - other small cleanups -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEzv7L6UO9uDPlPSfHEsHwGGHeVUoFAmLTudcACgkQEsHwGGHe VUrY4BAAtWm7wC6T8rzovbsyticj6kcehRMBEXxtlEP5LOeltR0dbNaIGskrS2Li Q9YxxtQhbZPXqzqB+xeHVhDPThzsd3+wRvvetmR4fW/c3XCYr+fLLFjHj0NEvX0P lQzuY8GKWGU/QTrjKSKclGvqyB692Fvdu4YImlnrGSbR6ywwVttditd3YNJR0w1q 7S4zq90uwWuX6cTLqXIcbKbhssOjcR1Agj9+bE8i+rzyB2VtNoihJCJh0pTJAn3P RaXnxI/7J6Y+5imPf5/ywu8gxhvGBTy5MU/1v2pw939EurU9tmhVkNVWdO2g/qYY V+Y1nj9xV0ucL4hlUBqAFdM+5jFC89Ey1X2tSgUgSl+44L/d8IIjVCp6inVoyCzE Olbc6q7A/V8PNXfo4g6gDwVc3Ii53Fwgtu8xVHkwPGfjly6+yZ9O/RUBXcBAOnpU jfS9LSc/Ro7kxqFy32beUgB7wwhMpkYuHe6ECxrvXj1IK13y3OkdxFzm03ty7S/E BwjrkltDia9BQ6i4Ywy+qSBYkSH6+sxxt4pboB+ft6/p2JIw4YJIp9PRqzPAG0jx JTjcZ9YAr7zPNlWp5e30BjGawgbuKPq0wkF1r6QD+3VzNf9+SSDmtkYGWeAyTTP2 SkzLy5QCNBTeeq0FZVYZFm/vcF7wccQhQdwNcezxygKAmihH0xw= =ND3p -----END PGP SIGNATURE----- Merge tag 'x86_urgent_for_v5.19_rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull x86 fixes from Borislav Petkov: - Improve the check whether the kernel supports WP mappings so that it can accomodate a XenPV guest due to how the latter is setting up the PAT machinery - Now that the retbleed nightmare is public, here's the first round of fallout fixes: * Fix a build failure on 32-bit due to missing include * Remove an untraining point in espfix64 return path * other small cleanups * tag 'x86_urgent_for_v5.19_rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: x86/bugs: Remove apostrophe typo um: Add missing apply_returns() x86/entry: Remove UNTRAIN_RET from native_irq_return_ldt x86/bugs: Mark retbleed_strings static x86/pat: Fix x86_has_pat_wp() x86/asm/32: Fix ANNOTATE_UNRET_SAFE use on 32-bit
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commit
59c80f053d
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@ -432,6 +432,10 @@ void apply_retpolines(s32 *start, s32 *end)
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{
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}
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void apply_returns(s32 *start, s32 *end)
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{
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}
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void apply_alternatives(struct alt_instr *start, struct alt_instr *end)
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{
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}
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@ -727,7 +727,6 @@ native_irq_return_ldt:
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pushq %rdi /* Stash user RDI */
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swapgs /* to kernel GS */
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SWITCH_TO_KERNEL_CR3 scratch_reg=%rdi /* to kernel CR3 */
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UNTRAIN_RET
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movq PER_CPU_VAR(espfix_waddr), %rdi
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movq %rax, (0*8)(%rdi) /* user RAX */
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@ -793,7 +793,7 @@ enum retbleed_mitigation_cmd {
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RETBLEED_CMD_IBPB,
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};
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const char * const retbleed_strings[] = {
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static const char * const retbleed_strings[] = {
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[RETBLEED_MITIGATION_NONE] = "Vulnerable",
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[RETBLEED_MITIGATION_UNRET] = "Mitigation: untrained return thunk",
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[RETBLEED_MITIGATION_IBPB] = "Mitigation: IBPB",
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@ -1181,7 +1181,7 @@ spectre_v2_user_select_mitigation(void)
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if (retbleed_mitigation == RETBLEED_MITIGATION_UNRET) {
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if (mode != SPECTRE_V2_USER_STRICT &&
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mode != SPECTRE_V2_USER_STRICT_PREFERRED)
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pr_info("Selecting STIBP always-on mode to complement retbleed mitigation'\n");
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pr_info("Selecting STIBP always-on mode to complement retbleed mitigation\n");
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mode = SPECTRE_V2_USER_STRICT_PREFERRED;
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}
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@ -23,6 +23,7 @@
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#include <asm/cpufeatures.h>
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#include <asm/percpu.h>
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#include <asm/nops.h>
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#include <asm/nospec-branch.h>
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#include <asm/bootparam.h>
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#include <asm/export.h>
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#include <asm/pgtable_32.h>
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@ -77,10 +77,20 @@ static uint8_t __pte2cachemode_tbl[8] = {
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[__pte2cm_idx(_PAGE_PWT | _PAGE_PCD | _PAGE_PAT)] = _PAGE_CACHE_MODE_UC,
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};
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/* Check that the write-protect PAT entry is set for write-protect */
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/*
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* Check that the write-protect PAT entry is set for write-protect.
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* To do this without making assumptions how PAT has been set up (Xen has
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* another layout than the kernel), translate the _PAGE_CACHE_MODE_WP cache
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* mode via the __cachemode2pte_tbl[] into protection bits (those protection
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* bits will select a cache mode of WP or better), and then translate the
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* protection bits back into the cache mode using __pte2cm_idx() and the
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* __pte2cachemode_tbl[] array. This will return the really used cache mode.
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*/
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bool x86_has_pat_wp(void)
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{
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return __pte2cachemode_tbl[_PAGE_CACHE_MODE_WP] == _PAGE_CACHE_MODE_WP;
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uint16_t prot = __cachemode2pte_tbl[_PAGE_CACHE_MODE_WP];
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return __pte2cachemode_tbl[__pte2cm_idx(prot)] == _PAGE_CACHE_MODE_WP;
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}
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enum page_cache_mode pgprot2cachemode(pgprot_t pgprot)
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