arm64: dts: st: introduce stm32mp25 SoCs family
STM32MP25 family is composed of 4 SoCs defined as following: -STM32MP251: common part composed of 1*Cortex-A35, common peripherals like SDMMC, UART, SPI, I2C, PCIe, USB3, parallel and DSI display, 1*ETH ... -STM32MP253: STM32MP251 + 1*Cortex-A35 (dual CPU), a second ETH, CAN-FD and LVDS display. -STM32MP255: STM32MP253 + GPU/AI and video encode/decode. -STM32MP257: STM32MP255 + ETH TSN switch (2+1 ports). A second diversity layer exists for security features/ A35 frequency: -STM32MP25xY, "Y" gives information: -Y = A means A35@1.2GHz + no cryp IP and no secure boot. -Y = C means A35@1.2GHz + cryp IP and secure boot. -Y = D means A35@1.5GHz + no cryp IP and no secure boot. -Y = F means A35@1.5GHz + cryp IP and secure boot. Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
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Alexandre Torgue
parent
9e4e24414c
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5d30d03aaf
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// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
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/*
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* Copyright (C) STMicroelectronics 2023 - All Rights Reserved
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* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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#address-cells = <2>;
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#size-cells = <2>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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compatible = "arm,cortex-a35";
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device_type = "cpu";
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reg = <0>;
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enable-method = "psci";
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};
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};
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arm-pmu {
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compatible = "arm,cortex-a35-pmu";
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interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-affinity = <&cpu0>;
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interrupt-parent = <&intc>;
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};
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clocks {
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ck_flexgen_08: ck-flexgen-08 {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <100000000>;
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};
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ck_flexgen_51: ck-flexgen-51 {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <200000000>;
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};
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ck_icn_ls_mcu: ck-icn-ls-mcu {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <200000000>;
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};
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};
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firmware {
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optee {
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compatible = "linaro,optee-tz";
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method = "smc";
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};
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scmi {
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compatible = "linaro,scmi-optee";
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#address-cells = <1>;
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#size-cells = <0>;
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linaro,optee-channel-id = <0>;
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scmi_clk: protocol@14 {
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reg = <0x14>;
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#clock-cells = <1>;
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};
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scmi_reset: protocol@16 {
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reg = <0x16>;
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#reset-cells = <1>;
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};
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};
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};
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intc: interrupt-controller@4ac00000 {
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compatible = "arm,cortex-a7-gic";
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#interrupt-cells = <3>;
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#address-cells = <1>;
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interrupt-controller;
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reg = <0x0 0x4ac10000 0x0 0x1000>,
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<0x0 0x4ac20000 0x0 0x2000>,
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<0x0 0x4ac40000 0x0 0x2000>,
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<0x0 0x4ac60000 0x0 0x2000>;
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};
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupt-parent = <&intc>;
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
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always-on;
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};
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soc@0 {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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interrupt-parent = <&intc>;
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ranges = <0x0 0x0 0x0 0x80000000>;
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rifsc: rifsc-bus@42080000 {
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compatible = "simple-bus";
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reg = <0x42080000 0x1000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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usart2: serial@400e0000 {
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compatible = "st,stm32h7-uart";
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reg = <0x400e0000 0x400>;
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interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ck_flexgen_08>;
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status = "disabled";
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};
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};
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syscfg: syscon@44230000 {
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compatible = "st,stm32mp25-syscfg", "syscon";
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reg = <0x44230000 0x10000>;
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};
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pinctrl: pinctrl@44240000 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "st,stm32mp257-pinctrl";
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ranges = <0 0x44240000 0xa0400>;
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pins-are-numbered;
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gpioa: gpio@44240000 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x0 0x400>;
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clocks = <&ck_icn_ls_mcu>;
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st,bank-name = "GPIOA";
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status = "disabled";
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};
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gpiob: gpio@44250000 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x10000 0x400>;
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clocks = <&ck_icn_ls_mcu>;
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st,bank-name = "GPIOB";
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status = "disabled";
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};
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gpioc: gpio@44260000 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x20000 0x400>;
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clocks = <&ck_icn_ls_mcu>;
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st,bank-name = "GPIOC";
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status = "disabled";
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};
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gpiod: gpio@44270000 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x30000 0x400>;
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clocks = <&ck_icn_ls_mcu>;
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st,bank-name = "GPIOD";
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status = "disabled";
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};
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gpioe: gpio@44280000 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x40000 0x400>;
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clocks = <&ck_icn_ls_mcu>;
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st,bank-name = "GPIOE";
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status = "disabled";
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};
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gpiof: gpio@44290000 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x50000 0x400>;
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clocks = <&ck_icn_ls_mcu>;
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st,bank-name = "GPIOF";
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status = "disabled";
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};
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gpiog: gpio@442a0000 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x60000 0x400>;
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clocks = <&ck_icn_ls_mcu>;
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st,bank-name = "GPIOG";
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status = "disabled";
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};
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gpioh: gpio@442b0000 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x70000 0x400>;
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clocks = <&ck_icn_ls_mcu>;
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st,bank-name = "GPIOH";
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status = "disabled";
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};
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gpioi: gpio@442c0000 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x80000 0x400>;
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clocks = <&ck_icn_ls_mcu>;
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st,bank-name = "GPIOI";
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status = "disabled";
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};
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gpioj: gpio@442d0000 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x90000 0x400>;
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clocks = <&ck_icn_ls_mcu>;
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st,bank-name = "GPIOJ";
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status = "disabled";
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};
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gpiok: gpio@442e0000 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0xa0000 0x400>;
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clocks = <&ck_icn_ls_mcu>;
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st,bank-name = "GPIOK";
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status = "disabled";
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};
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};
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pinctrl_z: pinctrl@46200000 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "st,stm32mp257-z-pinctrl";
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ranges = <0 0x46200000 0x400>;
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pins-are-numbered;
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gpioz: gpio@46200000 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0 0x400>;
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clocks = <&ck_icn_ls_mcu>;
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st,bank-name = "GPIOZ";
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st,bank-ioport = <11>;
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status = "disabled";
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};
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};
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};
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};
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@ -0,0 +1,23 @@
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// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
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/*
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* Copyright (C) STMicroelectronics 2023 - All Rights Reserved
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* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
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*/
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#include "stm32mp251.dtsi"
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/ {
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cpus {
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cpu1: cpu@1 {
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compatible = "arm,cortex-a35";
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device_type = "cpu";
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reg = <1>;
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enable-method = "psci";
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};
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};
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arm-pmu {
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interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-affinity = <&cpu0>, <&cpu1>;
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};
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};
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// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
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/*
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* Copyright (C) STMicroelectronics 2023 - All Rights Reserved
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* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
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*/
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#include "stm32mp253.dtsi"
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/ {
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};
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@ -0,0 +1,9 @@
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// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
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/*
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* Copyright (C) STMicroelectronics 2023 - All Rights Reserved
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* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
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*/
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#include "stm32mp255.dtsi"
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/ {
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};
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@ -0,0 +1,8 @@
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// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
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/*
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* Copyright (C) STMicroelectronics 2023 - All Rights Reserved
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* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
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*/
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/ {
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};
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@ -0,0 +1,8 @@
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// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
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/*
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* Copyright (C) STMicroelectronics 2023 - All Rights Reserved
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* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
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*/
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/ {
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};
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